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TAS5028A 8 channel digital audio pwm processor 2004 dav ? digital audio/speaker data manual sles120 tm
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2004, texas instruments incorporated
contents iii september 2004 sles120 contents section page 1 introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 TAS5028A system diagrams 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 TAS5028A features 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 audio input/output 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 audio processing 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 pwm processing 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 general features 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 physical characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 terminal assignments 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 ordering information 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 terminal descriptions 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 TAS5028A functional description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 power supply 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 clock, pll, and serial data interface 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 i 2 c serial control interface 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 device control 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 digital audio processor (dap) 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 TAS5028A dap architecture 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 TAS5028A dap architecture diagrams 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 i 2 c coefficient number formats 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 input crossbar mixer 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 bass and treble controls 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 volume, auto mute, and mute 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1 auto mute and mute 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 output mixer 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 pwm 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 dc blocking (high-pass enable / disable) 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.2 de-emphasis filter 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.3 am interference avoidance 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TAS5028A controls and status 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 i2c status registers 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 general status register (0x01) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 error status register (0x02) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 TAS5028A pin controls 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 reset (reset ) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 power down (pdn ) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 backend error (bknd_err ) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 speaker/headphone selector (hp_sel ) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 mute (mute ) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 device configuration controls 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 channel configuration registers 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 headphone configuration registers 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 audio system configurations 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 recovery from clock error 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 volume and mute update rate 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 modulation index limit 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
contents iv september 2004 sles120 2.3.7 inter-channel delay 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 master clock and serial data rate controls 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 pll operation 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 bank controls 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 manual bank selection 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 automatic bank selection 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 bank set 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 bank switch timeline 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.5 bank switching example 1 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.6 bank switching example 2 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical specifications 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 absolute maximum ratings 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 dynamic performance (at recommended operating conditions at 25 c) 35 . . . . . . . . . . . . . . . . . . . . 3.3 recommended operating conditions (over 0 c to 70 c) 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 electrical characteristics over recommended operating conditions 36 . . . . . . . . . . . . . . . . . . . . . . . . 3.5 pwm operation at recommended operating conditions over 0 c to 70 c 36 . . . . . . . . . . . . . . . . . . . 3.6 switching characteristics 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 clock signals over recommended operating conditions 36 . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 serial audio port 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 i 2 c serial control port operation 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 reset timing (reset ) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 power-down (pdn ) timing 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 backend error (bknd_err ) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 mute timing?mute 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8 headphone select (hp_sel ) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9 volume control 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 serial audio interface control and timing 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 i 2 s timing 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 left justified 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 right justified 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 i2c serial control interface (slave address 0x36) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 general i 2 c operation 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 single and multiple byte transfers 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 single byte write 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 multiple byte write 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 incremental multiple byte write 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 single byte read 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 multiple byte read 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial control i 2 c register summary 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial control interface register definitions 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 clock control register (0x00) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 general status register 0 (0x01) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 error status register (0x02) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 system control register 1 (0x03) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 system control register 2 (0x04) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 channel configuration control register (0x05 ? x0c) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 headphone configuration control register (0x0d) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 serial data interface control register (0x0e) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 soft mute register (0x0f) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of illustrations v september 2004 sles120 6.10 automute control register(0x14) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 automute pwm threshold and backend reset period (0x15) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 modulation index limit register (0x16) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 interchannel channel delay registers (0x1b ? 0x22) and offset register (0x23) 58 . . . . . . . . . . . . . . 6.14 bank switching command (0x40) 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 input mixer registers (0x41 ? 0x48, channels 1 ? 8) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 bass and treble bypass register (0x89 ? 0x90, channels 1 ? 8) 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 8x2 output mixer registers (0xaa ? 0xaf) 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 8x3 output mixer registers (0xb0 ? 0xb1) 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 volume treble and bass slew rates (0xd0) 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 volume registers (0xd1 ? 0xd9) 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21 bass filter set register (0xda) 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22 bass filter index register (0xdb) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23 treble filter set register (0xdc) 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24 treble filter index (0xdd) 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25 am mode register (0xde) 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26 general control register (0xe0) 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27 incremental multiple write append register (0xfe) 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TAS5028A example application schematic 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of illustrations figure title page 1 ? 1 TAS5028A functional structure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 2 typical TAS5028A application (dvd receiver) 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 3 recommended TAS5028A + tas5121 channel configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 4 TAS5028A dap architecture with i2c registers (fs 96 khz) 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 5 TAS5028A architecture with i2c registers (fs = 176.4 khz or fs = 192 khz) 13 . . . . . . . . . . . . . . . . . . . . . . 1 ? 6 TAS5028A detailed channel processing 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 7 5.23 format 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 8 conversion weighting factors?5.23 format to floating point 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 9 alignment of 5.23 coefficient in 32-bit i 2 c word 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 10 25.23 format 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 11 alignment of 523 coefficient in 32-bit i 2 c word 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 12 alignment of 2523 coefficient in two 32-bit i 2 c words 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 13 TAS5028A digital audio processing 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 14 input crossbar mixer 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 15 auto mute threshold 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 16 output mixers 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 17 de-emphasis filter characteristics 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 18 block diagrams of typical systems requiring TAS5028A automatic am interference avoidance circuit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 slave mode serial data interface timing 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 scl and sda timing 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 start and stop conditions timing 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 reset timing 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of tables vi september 2004 sles120 3 ? 5 power-down timing 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 error recovery timing 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 mute timing 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 hp_sel timing 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9i 2 s format 64 fs format 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 left justified 64 fs format 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 11 right justified 64 fs format 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 typical i 2 c sequence 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 single byte write transfer 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 3 multiple byte write transfer 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 4 single byte read transfer 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 5 multiple byte read transfer 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table title page 1 ? 1 serial data formats 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 2 TAS5028A audio processing feature sets 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 3 bass and treble filter selections 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 4 linear gain step size 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 1 device outputs during reset 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 values set during reset 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 device outputs during power down 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 device outputs during backend error 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 description of the channel configuration registers (0x05 to 0x0c) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 recommended TAS5028A configurations for texas instruments power stages 29 . . . . . . . . . . . . . . . . . . . . . 2 ? 7 audio system configuration (general control register 0xe0) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 volume ramp rates in ms 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 inter-channel delay default values 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 clock control register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 2 general status register (0x01) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 3 error status register (0x02) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 4 system control register 1 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 5 system control register 2 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 6 channel configuration control registers 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 7 headphone configuration control register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 8 serial data interface control register format 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 9 soft mute register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 10 automute control register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 11 automute pwm threshold and backend reset period 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 12 modulation index limit register 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 13 interchannel channel delay registers 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 14 channel offset register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 15 bank switching command 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 16 input mixer registers format (0x41 ? 0x48, channels 1 ? 8) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 17 bass and treble bypass register format (0x89 ? 0x90) 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 18 output mixer control register format (upper 4 bytes) 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of tables vii september 2004 sles120 6 ? 19 output mixer control (lower 4 bytes) 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 20 output mixer control (upper 4 bytes) 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 21 output mixer control (middle 4 bytes) 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 22 output mixer control (lower 4 bytes) 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 23 volume gain update rate (slew rate) 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 24 treble and bass gain step size (slew rate) 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 25 volume registers 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 26 master and individual volume controls 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 27 channel 8 sub woofer 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 28 channel 6 and 5 (right and left lineout in six channel configuration right and left surround in eight channel configuration) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 29 channel 4 and 3 (right and left rear) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 30 channel 7, 2, 1 (center, right front, and left front) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 31 bass filter index register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 32 bass filter index 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 33 channel 8 sub woofer 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 34 channel 6 and 5 (right and left lineout in six channel configuration or right and left surround in eight channel configuration) 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 35 channel 4 and 3 (right and left rear) 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 36 channel 7, 2, 1 (center, right front, and left front) 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 37 treble filter index register 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 38 treble filter index 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 39 am mode register 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 40 am tuned frequency register in bcd mode (lower 2 bytes of 0xde) 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 41 am tuned frequency register in binary mode (lower 2 bytes of 0xde) 71 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 42 general control register 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of tables viii september 2004 sles120
introduction 1 sles112 ? june 2004 TAS5028A 1 introduction the TAS5028A is an eight channel digital pulse width modulator (pwm) that provides both advanced performance and a high level of system integration. the TAS5028A is designed to interface seamlessly with most audio digital signal processors. the TAS5028A automatically adjusts control configurations in response to clock and data rate changes and idle conditions. this enables the TAS5028A to provide an easy to use control interface with relaxed timing requirements. the TAS5028A can drive eight channels of h-bridge power stages. texas instruments h-bridge parts tas5111, tas51 12, or t as5182 + fets are designed to work seamlessly with the t as5028a. the t as5028a supports both single-ended or bridge tied load configurations. the TAS5028A also provides a high performance dif ferential output to drive an external differential input analog headphone amplifier (such as the tpa112). the TAS5028A?s uses an ad modulation operating at a 384-khz switching rate for 48-, 96-, and 192-khz data. the 8x oversampling combined with the 5 th order noise shaper provides a broad flat noise floor and excellent dynamic range from 20 hz to 20 khz. the TAS5028A is clock slave only device. the TAS5028A receives mclk, sclk and lrclk from other system components. the TAS5028A accepts master clock rates of 128, 192, 256, 384, 512, and 768 fs. the TAS5028A accepts a 64-fs bit clock. pwm_hpp& mr pwm_hpp & ml mclk xtl_ out xtl_ in pll_fltm pll_fltp osc cap sclk lrclk sdin1 sdin2 sdin3 sdin4 sda scl vr_pll avdd_pll avss_pll avdd_ref vbgap vra_pll vrd_pll dvdd dvss avdd avss pwm section serial cntrl if pwm ap& am7 center pwm ap& am4 r sur pwm ap& am3 l sur pwm ap& am8 sub woofer pwm ap& am1 l pwm ap& am2 r clock, pll, & serial data i/f pwm ap& am5 l back sur pwm l line out pwm ap& am6 r back sur pwm r line out 8 x 2 crossbar mixer soft tone soft tone soft tone soft tone soft tone soft tone soft tone soft tone 8 x 8 crossbar mixer digital audio processor valid system control dap control pwm control control output control 8 4 8 0 det 0 det 0 det 0 det 0 det 0 det 0 det 0 det 8 8 9 pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block pwm de emph interpo late ns src dc block volume control power supply soft vol soft vol soft vol soft vol soft vol soft vol soft vol soft vol 8 reset pdn mute hp_sel bknd_err figure 1 ? 1. TAS5028A functional structure
introduction 2 sles112 ? june 2004 TAS5028A 1.1 TAS5028A system diagrams typical applications for the t as5028a are 6- to 8-channel audio systems such as dvd receiver or av receiver. figure 1 ? 2 shows the basic system diagram of the dvd receiver. dvd loader power supply am fm tuner texas instruments digital audio amplifier mpeg decoder front-panel controls TAS5028A figure 1 ? 2. typical TAS5028A application (dvd receiver) figure 1 ? 3 shows the recommended channel configuration when using the TAS5028A with the tas5121 power stage. note that each channel is normally dedicated to a particular function. tas5121 + ? tas5121 + ? tas5121 + ? tas5121 + ? tas5121 + ? tas5121 + ? tas5121 + ? tas5121 + ? pwm_m_1 pwm_p_1 pwm_m_2 pwm_p_2 pwm_m_3 pwm_p_3 pwm_m_4 pwm_p_4 pwm_m_7 pwm_p_7 pwm_m_8 pwm_p_8 pwm_m_5 pwm_p_5 pwm_m_6 pwm_p_6 left right left surround center subwoofer right surround left back surround right back surround sdin1,2,3,4 (8 chan. pcm) clocks i2c control & status hw control & status pwm to analog (line level) pwm to analog (headphone level) headphone out right headphone out left pwm_hpml pwm_hppl pwm_hpmr pwm_hppr pwm_m_5 pwm_p_5 pwm_m_6 pwm_p_6 lineout right lineout left TAS5028A figure 1 ? 3. recommended TAS5028A + tas5121 channel configuration
introduction 3 sles112 ? june 2004 TAS5028A 1.2 TAS5028A features 1.2.1 audio input / output ? automatic master clock rate and data sample rate detection ? eight serial audio input channels ? eight pwm audio output channels configurable as six channels with stereo line out or eight channels ? line output is a pwm output to drive an external differential input operational amplifier ? headphone pwm output to drive an external differential amplifier like the tpa112 ? pwm outputs support single ended and bridge tied loads ? 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-khz sampling rates ? data formats: 16-, 20-, or 24-bit input data left, right and i 2 s, ? 64 x fs bit clock rate ? 128, 192, 256, 384, 512, and 768 x fs master clock rates (up to a maximum of 50 mhz) 1.2.2 audio processing ? 48-bit processing architecture with 76 bits of precision for most audio processing features ? volume control range +36 db to ? 127 db ? master volume control range of +18 db to ?100 db ? eight individual channel volume control range of +18-db to ? 127-db ? programmable soft volume and mute update rates ? four bass and treble tone controls with 18-db range, selectable corner frequencies, and 2 nd order slopes ? l, r, and c ? ls, rs ? lr, rr ? sub ? full 8x8 input crossbar mixer. each signal processing channel input can be any ratio of the eight input channels ? 8x2 output mixer ? channels 1 ? 6. each output can be any ratio of any two signal processed channels ? 8x3 output mixer ? channels 7 and 8. each output can be any ratio of any three signal processed channels ? three coefficient sets stored on the device can be selected manually or automatically (based on specific data rates) ? dc blocking filters ? able to support a variety of bass management algorithms
introduction 4 sles112 ? june 2004 TAS5028A 1.2.3 pwm processing ? 32-bit processing pwm architecture with 40 bits of precision ? 8x oversampling with 5 th order noise shaping at 32 ? 48 khz, 4x oversampling at 88.2 khz, and 96 khz and 2x oversampling at 176.4 khz and 192 khz ? >102-db dynamic range ? thd+n < 0.1% ? 20 ? 20-khz flat noise floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-khz data rates ? digital de-emphasis for 32-, 44.1-, and 48-khz data rates ? flexible automute logic with programmable threshold and duration for noise free operation ? intelligent am interference avoidance system provides clear am reception ? adjustable modulation limit 1.2.4 general features ? automated operation with an easy to use control interface ? i 2 c serial control slave interface ? integrated am interference avoidance circuitry ? single 3.3-v power supply ? 64-pin tqfp package ? 5-v tolerant inputs
introduction 5 sles112 ? june 2004 TAS5028A 1.3 physical characteristics 1.3.1 terminal assignments 17 vr_pwm pwm_p_4 pwm_m_4 pwm_p_3 pwm_m_3 pwm_p_2 pwm_m_2 pwm_p_1 pwm_m_1 valid dvss bknd_err dvdd dvss dvss vr_dig 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vra_pll pll_flt_ret pll_fltm pll_fltp avss avss vrd_pll avss_pll avdd_pll vbgap reset hp_sel pdn mute dvdd dvss 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 tqfp package (top view) vr_dpll osc_cap xtl_out xtl_in reserved reserved reserved sda scl lrclk sclk sdin4 sdin3 sdin2 sdin1 reserved reserved mclk pwm_hppr pwm_hpmr pwm_hppl pwm_hpml pwm_p_6 pwm_m_6 pwm_p_5 pwm_m_5 dvdd_pwm dvss_pwm pwm_p_8 pwm_m_8 pwm_p_7 pwm_m_7 1.3.2 ordering information t a plastic 64-pin pqfp (pn) 0 c to 70 c TAS5028Apag 1.3.3 terminal descriptions terminal i/o 5-v termin- description no. name i/o 5-v tolerant termin- ation description 1 vra_pll voltage reference for pll analog supply 1.8 v. a pin-out of the internally regulated 1.8-v power used by pll logic. a 0.1- f low esr capacitor should be connected between this terminal and avss_pll. this terminal must not be used to power external devices. 2 pll_flt_ret ao pll external filter return 3 pll_fltm ao pll negative input. connected to pll_flt_rtn via an rc network 4 pll_fltp ai pll positive input. connected to pll_flt_rtn via an rc network 5 avss p analog ground 6 avss p analog ground
introduction 6 sles112 ? june 2004 TAS5028A terminal description termin- ation 5-v tolerant i/o no. description termin- ation 5-v tolerant i/o name 7 vrd_pll p voltage reference for pll digital supply 1.8 v. a pin-out of the internally regulated 1.8-v power used by pll logic. a 0.1- f low esr capacitor should be connected between this terminal and avss_pll. this terminal must not be used to power external devices. 8 avss_pll p analog ground for pll. this terminal should reference the same ground as power terminal dvss, but to achieve low pll jitter; ground noise at this terminal must be minimized. the availability of the avss terminal allows a designer to use optimizing techniques such as star ground connections, separate ground planes, or other quiet ground distribution techniques to achieve a quiet ground reference at this terminal. 9 avdd_pll p 3.3-v analog power supply for pll this terminal can be connected to the same power source used to drive power terminal dvss, but to achieve low pll jitter, this terminal should be bypassed to avss_pll with a 0.1- f low-esr capacitor. 10 vbgap p band gap voltage reference. a pin-out of the internally regulated 1.2-v reference. typically has a 1-nf low esr capacitor between vbgap and avss_pll. this terminal must not be used to power external devices. 11 reset di 5 v pullup system reset input, active low. a system reset is generated by applying a logic low to this terminal. reset is an asynchronous control signal that restores the TAS5028A to its default conditions, sets the valid output low, and places the pwm in the hard mute (m) state. master volume is immediately set to full attenuation. upon the release of reset , if pdn is high, the system performs a 4 ? 5 ms. device initialization and sets the volume at mute. 12 hp_sel di 5 v pullup headphone in/out selector. when a logic low is applied, the headphone is selected (speakers are off). when a logic high is applied, speakers are selected ? headphone is off. 13 pdn di 5 v pullup power down, active low. pdn powers down all logic and stops all clocks whenever a logic low is applied. the internal parameters are preserved through a power down cycle, as long as a reset is not active. the duration for system recovery from power down is 100 ms. 14 mute di 5 v pullup soft mute of outputs, active low (muted signal = a logic low, normal operation = a logic high) the mute control provides a noiseless volume ramp to silence. releasing mute provides a noiseless ramp to previous volume. 15 dvdd p digital power 3.3-v supply for digital core and most of i/o buffers 16 dvss p digital ground for digital core and most of i/o buffers 17 vr_dpll p voltage reference for digital pll supply 1.8 v. a pin-out of the internally regulated 1.8-v power used by digital pll logic. a 0.1 ? f low esr capacitor should be connected between this terminal and dvss_core. this terminal must not be used to power external devices. 18 osc_cap ao oscillator capacitor 19 xtl_out ao xtl_out and xtl_in are the only lvcmos terminals on the device. they provide a reference clock for the TAS5028A via use of an external fundamental mode crystal. xtl_out is the 1.8-v output drive to the crystal. see note 4 for the recommended crystal type. 20 xtl_in ai xtl_out and xtl_in are the only lvcmos terminals on the device. they provide a reference clock for the TAS5028A via use of an external fundamental mode crystal. xtl_in is the 1.8-v input port for the oscillator circuit. see note 4 for the recommended crystal type. 21 reserved connect to digital ground 22 reserved connect to digital ground 23 reserved connect to digital ground 24 sda dio 5 v i 2 c serial control data interface input / output 25 scl di 5 v i 2 c serial control clock input output 26 lrclk di 5 v serial audio data left / right clock (sampling rate clock) 27 sclk di 5 v serial audio data clock (shift clock) sclkin is the serial audio port (sap) input data bit clock that is supplied to the serial bit clock to other i 2 s bus.
introduction 7 sles112 ? june 2004 TAS5028A terminal description termin- ation 5-v tolerant i/o no. description termin- ation 5-v tolerant i/o name 28 sdin4 di 5 v pulldown serial audio data 4 input is one of the serial data input ports. sdin4 supports four discrete (stereo) data formats and is capable of inputting data at 64 fs. 29 sdin3 di 5 v pulldown serial audio data 3 input is one of the serial data input ports. sdin3 supports four discrete (stereo) data formats and is capable of inputting data at 64 fs. 30 sdin2 di 5 v pulldown serial audio data 2 input is one of the serial data input ports. sdin2 supports four discrete (stereo) data formats and is capable of inputting data at 64 fs. 31 sdin1 di 5 v pulldown serial audio data 1 input is one of the serial data input ports. sdin1 supports four discrete (stereo) data formats and is capable of inputting data at 64 fs. 32 reserved o 33 vr_dig p voltage reference for digital core supply 1.8 v. a pin-out of the internally regulated 1.8-v power used by digital core logic. a 0.47- f low esr capacitor should be connected between this terminal and dvss. this terminal must not be used to power external devices 34 dvss p digital ground 35 dvss p digital ground 36 dvdd p 3.3-v digital power supply 37 bknd_err di pullup active low. a backend error sequence is generated by applying logic low to this terminal. the bknd_err results in all system parameters unaffected, while all h-bridge drive signals going to a hard mute (m) state. 38 dvss p digital ground 39 valid do output indicating validity of pwm outputs active high 40 pwm_m_1 do pwm 1 output (differential ?) 41 pwm_p_1 do pwm 1 output (differential +) 42 pwm_m_2 do pwm 2 output (differential ?) 43 pwm_p_2 do pwm 2 output (differential +) 44 pwm_m_3 do pwm 3 output (differential ?) 45 pwm_p_3 do pwm 3 output (differential +) 46 pwm_m_4 do pwm 4 output (differential ?) 47 pwm_p_4 do pwm 4 output (differential +) 48 vr_pwm p voltage reference for digital pwm core supply 1.8 v. a pin-out of the internally regulated 1.8-v power used by digital pwm core logic. a 0.1- f low esr capacitor should be connected between this terminal and dvss_pwm. this terminal must not be used to power external devices. 49 pwm_m_7 do pwm 7 (line out l) output (differential ?) 50 pwm_p_7 do pwm 7 (line out l) output (differential +) 51 pwm_m_8 do pwm 8 (line out r) output (differential ?) 52 pwm_p_8 do pwm 8 (line out r) output (differential +) 53 dvss_pwm p digital ground for pwm 54 dvdd_pwm p 3.3-v digital power supply for pwm 55 pwm_m_5 do pwm 5 output (differential ?) 56 pwm_p_5 do pwm 5 output (differential +) 57 pwm_m_6 do pwm 6 output (differential ?) 58 pwm_p_6 do pwm 6 output (differential +) 59 pwm_hpml do pwm left channel headphone (differential ?) 60 pwm_hppl do pwm left channel headphone (differential +) 61 pwm_hpmr do pwm right channel headphone (differential ?) 62 pwm_hppr do pwm right channel headphone (differential +)
introduction 8 sles112 ? june 2004 TAS5028A terminal description termin- ation 5-v tolerant i/o no. description termin- ation 5-v tolerant i/o name 63 mclk di 5 v pulldown mclk is a 3.3-v clock master clock input. the input frequency of this clock can range from 4 mhz to 50 mhz. 64 reserved connect to digital ground notes: 1. type: a = analog; d = 3.3-v digital; p = power / ground / decoupling; i = input; o = output 2. all pullups are 20- a weak pullups and all pulldowns are 20- a weak pull downs. the pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). devices that drive inputs with pull ups must be able to sink 20 a, while maintaining a logic 0 drive level. devices that drive inputs with pulldowns must be able to source 20 a, while maintaining a logic ?1? drive level. 3. if desired, low esr capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. paral leling capacitors of equal value provide an extended high frequency supply decoupling. this approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values. 4. 13.5-mhz crystal (hcm49) 1.4 TAS5028A functional description figure 1 ? 4 shows the TAS5028A functional structure. the next sections describe the TAS5028A functional blocks: ? power supply ? clock, pll, and serial data interface ? serial control interface ? device control ? digital audio processor (dap) ? pulse width modulation (pwm) processor 1.4.1 power supply the power supply section contains supply regulators that provide analog and digital regulated power for various sections of the t as5028a. the analog supply supports the analog pll, while digital supplies support the digital pll, the digital audio processor (dap), the pulse width modulator (pwm), and the output control (reclocker). the regulators can also be turned off when terminals reset and pdn are both low. 1.4.2 clock, pll, and serial data interface the TAS5028A is a clock slave only device and it requires the use of an external 13.5 mhz crystal. it accepts mclk, sclk, and lrclk as inputs only. the TAS5028A uses the external crystal to provide a time base for: ? continuous data and clock error detection and management ? automatic data rate detection and configuration ? automatic mclk rate detection and configuration (automatic bank switching) ? supporting i 2 c operation/ communication while mclk is absent the TAS5028A automatically handles clock errors, data rate changes, and master clock frequency changes without requiring intervention from an external system controller. this feature significantly reduces system complexity and design.
introduction 9 sles112 ? june 2004 TAS5028A 1.4.2.1 serial audio interface the TAS5028A operates as a slave only / receive only serial data interface in all modes. the t as5028a has four pcm serial data interfaces to permit eight channels of digital data to be received though the sdin1, sdin2, sdin3, and sdin4 inputs. the serial audio data is in msb first, two?s complement format. the serial data input interface of the TAS5028A can be configured in right justified, i 2 s, or left-justified modes. the serial data interface format is specified using the i 2 c data interface control register. the supported formats and word lengths are shown in table 1 ? 1. table 1 ? 1. serial data formats receive serial data interface format word lengths right justified 16 right justified 20 right justified 24 i2s 16 i2s 20 i2s 24 left justified 16 left justified 20 left justified 24 serial data is input on sdin1, sdin2, sdin3, and sdin4. the TAS5028A accepts 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-khz serial data in 16-, 20-, or 24-bit data in left, right, and i 2 s serial data formats using a 64-fs sclk clock and a 128, 192, 256, 384, 512, or 768 x fs mclk rates (up to a maximum of 50 mhz). the parameters of this clock and serial data interface are i 2 c configurable. 1.4.3 i 2 c serial control interface the TAS5028A has an i 2 c serial control slave interface (address 0x36) to receive commands from a system controller. the serial control interface supports both normal-speed (100 khz) and high-speed (400 khz) operations without wait states. since the TAS5028A has a crystal time base, this interface operates even when mclk is absent. the serial control interface supports both single byte and multi-byte read / write operations for status registers and the general control registers associated with the pwm. however, for the dap data processing registers, the serial control interface also supports multiple byte (4 byte) write operations. the i 2 c supports a special mode which permits i 2 c write operations to be broken up into multiple data write operations that are multiples of 4 data bytes. these are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data. this permits the system to incrementally write large register values without blocking other i 2 c transactions. in order to use this feature, the first chunk of data is written to the target i 2 c address and each chunk of subsequent data is written to a special append register (0xfe), until all the data is written and a stop bit is sent. an incremental read operation is not supported. 1.4.4 device control the TAS5028A control section provides the control and sequencing for the TAS5028A. the device control provides both high and low level control for the serial control interface, clock and serial data interfaces, digital audio processor, and pulse width modulator sections. 1.4.5 digital audio processor (dap) the dap arithmetic unit is used to implement all audio processing functions ? soft volume, bass and treble processing, and input and output mixing. figure 1 ? 6 shows the TAS5028A dap architecture.
introduction 10 sles112 ? june 2004 TAS5028A the dap accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the pwm section. the dap supports two configurations, one for 32 ? khz to 96 ? khz data and one for 176.4 ? khz to 192 ? khz data. 1.4.5.1 TAS5028A audio processing configurations the 32 ? khz?96 ? khz configuration supports eight channels of data processing that can be configured as eight channels or six channels with two channels for separate stereo line outputs. the 176.4 ? 192 khz configuration supports three channels of signal processing with five channels passed though (or derived from the three processed channels). to efficiently support the processing requirements of both multi-channel 32 ? 96-khz data and the two channel 176.4 and 192-khz data, the TAS5028A supports separate audio processing features for 32 ?96-khz data rates and for 176.4 and 192 khz. see table 2 for a summary of TAS5028A processing feature sets. 1.4.5.2 TAS5028A audio signal processing functions the dap provides 7 primary signal processing functions. 1. the data processing input has a full 8x8 input crossbar mixer. this enables each input to be any ratio of the eight input channels. 2. two i 2 c programmable threshold detectors in each channel support automute. 3. four soft bass and treble tone controls with 18 db range, programmable corner frequencies, and 2nd order slopes. in 8-channel mode, bass and treble controls are normally configured as follows: a. bass and treble 1: channel 1 (left), channel 2 (right), and channel 7 (center) b. bass and treble 2: channel 3 (left surround) and channel 4 (right surround) c. bass and treble 3: channel 5 (left back surround) and channel 6 (right back surround) d. bass and treble 4: channel 8 (subwoofer) 4. individual channel and master volume controls. each control provides an adjustment range of +18 db to ?127 db. this permits a total volume device control range of +36 db to ?127 db plus mute. the master volume control can be configured to control six or eight channels. the dap soft volume and mute update interval is i 2 c programmable. the update is performed at a fixed rate regardless of the sample rate. 5. 8x2 output mixer (channels 1 ? 6). each output can be any ratio of any two signal processed channels. 6. 8x3 output mixer (channels 7 and 8). each output can be any ratio of any three signal processed channels. 7. the dap maintains three sets of coefficient banks that are used to maintain separate sets of sample rate dependent parameters for the tone controls in ram. these can be set to be automatically selected for one or more data sample rates or can be manually selected under i 2 c program control. this feature enables coef ficients for dif ferent sample rates to be stored in the TAS5028A and then select when needed.
introduction 11 sles112 ? june 2004 TAS5028A table 1 ? 2. TAS5028A audio processing feature sets feature 32 ? 96 khz 8 channel feature set 32 ? 96 khz 6 + 2 line out feature set 176.4- and 192-khz feature set signal processing channels 8 6 + 2 3 pass through channels n/a 5 master volume 1 for eight channels 1 for six channels 1 for three channels individual channel volume controls 8 3 bass and treble tone controls four bass and treble tone controls with 18 db range, programmable corner frequencies, and 2nd order slopes l, r and c (ch 1, 2, and 7) ls, rs (ch 3 and 4) lbs, rbs (ch 5 and 6) sub (ch 8) four bass and treble tone controls with 18 db range, programmable corner frequencies, and 2nd order slopes l, r and c (ch 1, 2, and 7) ls, rs (ch 3 and 4) sub, (ch 8) line l and r (ch 5 and 6) two bass and treble tone controls with 18 db range, programmable corner frequencies, and 2nd order slopes l and r (ch 1 and 2) sub (ch 8) input output mapping/mixing each of the eight signal-processing channels input can be any ratio of the eight input channels. each of the eight outputs can be any ratio of any two processed channels. each of the three signal-processing channels or the five pass-though channels inputs can be any ratio of the eight input channels. each of the eight outputs can be any ratio of any of the three processed or five bypass channels. dc blocking filters (implemented in pwm section) eight channels digital de-emphasis (implemented in pwm section) eight channels for 32 khz, 44.1 khz, and 48 khz six channels for 32 khz, 44.1 khz, and 48 khz n/a number of coefficient sets stored three additional coefficient sets can be stored in memory 1.5 TAS5028A dap architecture 1.5.1 TAS5028A dap architecture diagrams figure 1 ? 4 shows the TAS5028A dap architecture for fs = 96 khz. note the TAS5028A bass management architecture shown in channels 1, 2, 7, and 8. note that the i 2 c registers are shown to help the designer configure the TAS5028A. figure 1 ? 5 shows the TAS5028A architecture for fs = 176.4 khz or fs = 192 khz. note that only channels 1, 2, and 8 contain all the features. channels 3 ? 7 are pass-through except for master volume control. figure 1 ? 6 shows t as5028a detailed channel processing. the output mixer is 8x2 for channels 1 ? 6 and *x3 for channels 7 and 8.
introduction 12 sles112 ? june 2004 TAS5028A dap7 volume (0xd7) dap8 volume (0xd8) master vol (0xd9) a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h ip mixer 1 (i2c 0x41) a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h ip mixer 2 (i2c 0x42) ip mixer 3 (i2c 0x43) ip mixer 4 (i2c 0x44) ip mixer 5 (i2c 0x45) ip mixer 6 (i2c 0x46) ip mixer 7 (i2c 0x47) ip mixer 8 (i2c 0x48) bass & treble 1 (0xda ? 0xdd) l to pwm1 op mixer 1 (i2c 0xaa) 8x2 output mixer bass & treble 1 (0xda ? 0xdd) r to pwm2 op mixer 2 (i2c 0xab) 8x2 output mixer bass & treble 2 (0xda ? 0xdd) ls to pwm3 op mixer 3 (i2c 0xac) 8x2 output mixer bass & treble 2 (0xda ? 0xdd) rs to pwm4 op mixer 4 (i2c 0xad) 8x2 output mixer bass & treble 3 (0xda ? 0xdd) lbs to pwm5 op mixer 5 (i2c 0xae) 8x2 output mixer bass & treble 3 (0xda ? 0xdd) rbs to pwm6 op mixer 6 (i2c 0xaf) 8x2 output mixer bass & treble 1 (0xda ? 0xdd) c to pwm7 op mixer 7 (i2c 0xb0) 8x3 output mixer bass & treble 4 (0xda ? 0xdd) sub to pwm8 op mixer 8 (i2c 0xb1) 8x3 output mixer dap1 volume (0xd1) master vol (0xd9) dap2 volume (0xd2) master vol (0xd9) dap3 volume (0xd3) master vol (0xd9) dap4 volume (0xd4) master vol (0xd9) dap5 volume (0xd5) master vol (0xd9) dap6 volume (0xd6) master vol (0xd9) master vol (0xd9) sdin1 ? l(l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l(ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l(ls) sdin2 ? r(rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l(ls) sdin2 ? r (rs) sdin3 ? l(lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l(ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r(rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l(ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r(rbs) sdin4 ? l(c) sdin4 ? r (lfe) sdin1 ? l(l) sdin1 ? r(r) sdin2 ? l(ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r(rbs) sdin4 ? l (c) sdin4 ? r(lfe) default input is bold figure 1 ? 4. TAS5028A dap architecture with i 2 c registers (fs 96 khz)
introduction 13 sles112 ? june 2004 TAS5028A a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h ip mixer 1 (i2c 0x41) a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h ip mixer 2 (i2c 0x42) ip mixer 3 (i2c 0x43) ip mixer 4 (i2c 0x44) ip mixer 5 (i2c 0x45) ip mixer 6 (i2c 0x46) ip mixer 7 (i2c 0x47) ip mixer 8 (i2c 0x48) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) sdin1 ? l (l) sdin1 ? r (r) sdin2 ? l (ls) sdin2 ? r (rs) sdin3 ? l (lbs) sdin3 ? r (rbs) sdin4 ? l (c) sdin4 ? r (lfe) bass & treble 1 (0xda ? 0xdd) l to pwm1 op mixer 1 (i2c 0xaa) 8x2 output mixer bass & treble 1 (0xda ? 0xdd) r to pwm2 op mixer 2 (i2c 0xab) 8x2 output mixer ls to pwm3 op mixer 3 (i2c 0xac) 8x2 output mixer rs to pwm4 op mixer 4 (i2c 0xad) 8x2 output mixer lbs to pwm5 op mixer 5 (i2c 0xae) 8x2 output mixer rbs to pwm6 op mixer 6 (i2c 0xaf) 8x2 output mixer c to pwm7 op mixer 7 (i2c 0xb0) 8x3 output mixer bass & treble 4 (0xda ? 0xdd) sub to pwm8 op mixer 8 (i2c 0xb1) 8x3 output mixer dap1 volume (0xd1) master vol (0xd9) dap2 volume (0xd2) master vol (0xd9) dap8 volume (0xd8) master vol (0xd9) master vol (0xd9) master vol (0xd9) master vol (0xd9) master vol (0xd9) master vol (0xd9) default input is bold figure 1 ? 5. TAS5028A architecture with i 2 c registers (fs = 176.4 khz or fs = 192 khz)
introduction 14 sles112 ? june 2004 TAS5028A bass and treble input mixer trunc pwm proc volume a_to_ipmix b_to_ipmix a sdin1 b c_to_ipmix d_to_ipmix c sdin2 d e_to_ipmix f_to_ipmix e sdin3 f g_to_ipmix h_to_ipmix g sdin4 h left left left left right right right right channel volume master volume bass and treble bypass bass and treble in-line output gain output mixer sums any two or three channels pwm output one or two other channel outputs from seven available 32-bit figure 1 ? 6. TAS5028A detailed channel processing 1.5.2 i 2 c coefficient number formats the architecture of the TAS5028A is contained in rom resources within the TAS5028A and cannot be altered. however, mixer gain, level offset, and filter tap coefficients, which can be entered via the i 2 c bus interface, provide a user with the flexibility to set the TAS5028A to a configuration that achieves the system level goals. the firmware is executed in a 48-bit signed fixed-point arithmetic machine. the most significant bit of the 48-bit data path is a sign bit, and the 47 lower bits are data bits. mixer gain operations are implemented by multiplying a 48-bit signed data value by a 28-bit signed gain coefficient. the 76-bit signed output product is then truncated to a signed 48-bit number. level offset operations are implemented by adding a 48-bit signed offset coef ficient to a 48-bit signed data value. in most cases, if the addition results in overflowing the 48-bit signed number format, saturation logic is used. this means that if the summation results in a positive number that is greater than 0x7fff ffff ffff (the spaces are used to ease the reading of the hexadecimal number), the number is set to 0x7fff ffff ffff. if the summation results in a negative number that is less than 0x8000 0000 0000 0000, the number is set to 0x8000 0000 0000 0000. 1.5.2.1 28-bit 5.23 number format all mixer gain coefficients are 28-bit coefficients using a 5.23 number format. numbers formatted as 5.23 numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal point. this is shown in the figure 1 ? 7. 2 ? 23 bit s_xxxx.xxxx_xxxx_xxxx_xxxx_xxx 2 ? 4 bit 2 ? 1 bit 2 0 bit sign bit 2 3 bit figure 1 ? 7. 5.23 format
introduction 15 sles112 ? june 2004 TAS5028A the decimal value of a 5.23 format number can be found by following the weighting shown in figure 1 ? 8. if the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. if the most significant bit is a logic 1, then the number is a negative number. in this case every bit must be inverted, a 1 added to the result, and then the weighting shown in figure 1 ? 8 applied to obtain the magnitude of the negative number. (1 or 0) x 2 3 + (1 or 0) x 2 2 + + (1 or 0) x 2 0 + (1 or 0) x 2 ? 1 + + (1 or 0) x 2 ? 4 + + (1 or 0) x 2 ? 23 2 3 bit 2 2 bit 2 0 bit 2 ? 1 bit 2 ? 4 bit 2 ? 23 bit figure 1 ? 8. conversion weighting factors?5.23 format to floating point gain coefficients, entered via the i 2 c bus, must be entered as 32-bit binary numbers. the format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in figure 1 ? 9. u coefficient digit 8 u u u s x x x coefficient digit 7 x. x x x coefficient digit 6 x x x x coefficient digit 5 x x x x coefficient digit 4 x x x x coefficient digit 3 x x x x coefficient digit 2 x x x x coefficient digit 1 fraction digit 5 sign bit 0 fraction digit 6 fraction digit 4 fraction digit 3 fraction digit 2 fraction digit 1 integer digit 1 u = unused or don?t care bits digit = hexadecimal digit figure 1 ? 9. alignment of 5.23 coefficient in 32-bit i 2 c word as figure 1 ? 9 shows, the hex value of the integer part of the gain coefficient cannot be concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit i 2 c coefficient. the reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. in the same way, the fractional part occupies the lower 3 bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the zero-valued most significant hex digit). 1.5.2.2 48-bit 25.23 number format all level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. numbers formatted as 25.23 numbers means that there are 25 bits to the left of the decimal point and 23 bits to the right of the decimal point. this is shown in figure 1 ? 10.
introduction 16 sles112 ? june 2004 TAS5028A 2 ? 23 bit s_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx 2 0 bit 2 16 bit 2 22 bit sign bit 2 23 bit 2 ? 1 bit 2 ? 10 bit figure 1 ? 10. 25.23 format figure 1 ? 11 shows the derivation of the decimal value of a 48-bit 25.23 format number. (1 or 0) x 2 23 + (1 or 0) x 2 22 + + (1 or 0) x 2 0 + (1 or 0) x 2 ? 1 + + (1 or 0) x 2 ? 23 2 23 bit 2 22 bit 2 0 bit 2 ? 1 bit 2 ? 23 bit figure 1 ? 11. alignment of 5.23 coefficient in 32-bit i 2 c word two 32-bit words must be sent over the i 2 c bus to download a level or threshold coefficient into the t as5028a. the alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) i 2 c word is shown in figure 1 ? 12.
introduction 17 sles112 ? june 2004 TAS5028A u coefficient digit 16 u u u u u u u coefficient digit 15 u u u u coefficient digit 14 u u u u coefficient digit 13 s x x x coefficient digit 12 x x x x coefficient digit 11 x x x x coefficient digit 10 x x x x coefficient digit 9 word 1 (most significant word) integer digit 3 integer digit 4 (bits 2 3 ? 2 1 ) integer digit 2 integer digit 1 sign bit x coefficient digit 8 x x x x x x x coefficient digit 7 x. x x x coefficient digit 6 x x x x coefficient digit 5 x x x x coefficient digit 4 x x x x coefficient digit 3 x x x x coefficient digit 2 x x x x coefficient digit 1 word 2 (least significant word) fraction digit 5 integer digit 4 (bit 2 0 ) 0 fraction digit 6 fraction digit 4 fraction digit 3 fraction digit 2 fraction digit 1 integer digit 6 integer digit 5 u = unused or don?t care bits digit = hexadecimal digit figure 1 ? 12. alignment of 25.23 coefficient in two 32-bit i 2 c words 1.5.2.3 TAS5028A audio processing the TAS5028A digital audio processing is designed such that noise produced by filter operations is maintained below the smallest signal amplitude of interest, as shown in figure 1 ? 13. the t as5028a achieves this by increasing the precision of the signal representation substantially above the number of bits that are absolutely necessary to represent the input signal. maximum signal amplitude signal bits output noise floor as a result of additional precision ideal input desired output reduced snr signal output noise floor with no additional precision possible outputs filter operation signal bits input overflow values retained by overflow bits figure 1 ? 13. TAS5028A digital audio processing
introduction 18 sles112 ? june 2004 TAS5028A similarly, the TAS5028A carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. the TAS5028A advanced digital audio processor achieves both of these important performance capabilities by using a high performance digital audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator. 1.6 input crossbar mixer the TAS5028A has a full 8x8 input crossbar mixer. this mixer permits each signal processing channel input to be any ratio of any of the eight input channels. the control parameters for the input crossbar mixer are programmable via the i 2 c interface. see section 6.15,. sum gain coefficient 28 48 input 1 gain coefficient 28 48 input 2 gain coefficient 28 48 input 8 48 48 48 figure 1 ? 14. input crossbar mixer 1.7 bass and treble controls from 32-khz to 96-khz data, the TAS5028A has four bass and treble tone controls. each control has a 18-db control range with selectable corner frequencies and 2nd order slopes. these controls operate four channel groups: ? l, r, and c (channels 1, 2, and 7) ? ls, rs (channels 3 and 4) ? lbs, rbs (or alternately called l and r lineout.) (channels 5 and 6) ? sub (channel 8) for 176.4 khz and 192 khz data, the TAS5028A has two bass and treble tone controls. each control has a 18-db i 2 c control range with selectable corner frequencies and 2nd order slopes. these controls operate two channel groups: ? l and r ? sub the bass and treble filters utilize a soft update rate that does not produce artifacts during adjustment.
introduction 19 sles112 ? june 2004 TAS5028A table 1 ? 3. bass and treble filter selections fs (khz) 3-db corner frequencies filter set 1 filter set 1 filter set 2 filter set 2 filter set 3 filter set 3 filter set 4 filter set 4 filter set 5 filter set 5 bass treble bass treble bass treble bass treble bass treble 32 42 917 83 1833 125 3000 146 3667 167 4333 38 49 1088 99 2177 148 3562 173 4354 198 5146 44.1 57 1263 115 2527 172 4134 201 5053 230 5972 48 63 1375 125 2750 188 4500 219 5500 250 6500 88.2 115 2527 230 5053 345 8269 402 10106 459 11944 96 125 2750 250 5500 375 9000 438 11000 500 13000 176.4 230 5053 459 10106 689 16538 804 20213 919 23888 192 250 5500 500 11000 750 18000 875 22000 1000 26000 the i 2 c registers that control bass and treble are: ? bass and treble by-pass register (0x89 ? 0x90, channels 1 ? 8) ? bass and treble slew rates (0xd0) ? bass filter sets 1 ? 5 (0xda) ? bass filter index (0xdb) ? treble filter sets 1 ? 5 (0xdc) ? treble filter index (0xdd) 1.8 volume, automute, and mute the TAS5028A provides individual channel and master volume controls. each control provides an adjustment range of +18.0618 db to ?100 db in 0.25 db increments. this permits a total volume device control range of +36 db to ?100 db plus mute. the master volume control can be configured to control six or eight channels. the TAS5028A has a master soft mute control that can be enabled by a terminal or i 2 c command. the device also has individual channel soft mute controls that can are enabled via i 2 c. the soft volume and mute update rates are programmable. the soft adjustments are performed using a soft gain linear update with an i 2 c programmable linear step size at a fixed temporal rate. the linear soft gain step size can be varied from 0.5 to 0.003906. table 1 ? 4. linear gain step size step size (gain) 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 0.003906 time to go from 36.124 db to ? 127 db in ms 10.67 21.33 42.67 85.34 170.67 341.35 682.70 1365.4 time to go from 18.062 db to ? 127 db in ms 1.33 2.67 5.33 10.67 21.33 42.67 85.33 170.67 time to go from 0 db to ? 127 db in ms 0.17 0.33 0.67 1.33 2.67 5.33 10.67 21.33
introduction 20 sles112 ? june 2004 TAS5028A 1.8.1 automute and mute the TAS5028A has individual channel automute controls that are enabled via the i 2 c interface. there are two separate detectors used to trigger the automute: ? input automute: all channels are muted when all 8 inputs to the TAS5028A are less in magnitude than the input threshold value for a programmable amount of time. ? output automute: a single channel is muted when the output of the dap section is less in magnitude than the input threshold value for a programmable amount of time. the detection period and thresholds for these two detectors are the same. this time interval is selectable via i 2 c to be from 1 ms. to 110 ms. the increments of time are 1, 2, 3, 4, 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. this interval is independent of the sample rate. the default value is mask programmable. the input threshold value is an unsigned magnitude that is expressed as a bit position. this value is adjustable via i 2 c. the range of the input threshold adjustment is from below the lsb (bit position 0) to below bit position 12 in a 24 bit input data word (bit positions 8 to 20 in the dspe). this provides an input threshold that can be adjusted for 12 to 24 bits of data. the default value is mask programmable. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dvd data range cd data range threshold range 24-bit input 32-bit in dspe representation figure 1 ? 15. automute threshold the automute state is exited when the TAS5028A receives one sample that is greater that the output threshold. the output threshold can be one of two values: ? equal to the input threshold ? 6 db (one bit position) greater than the input threshold the value for the output threshold is selectable via i 2 c. the default value is mask programmable. the system latency enables the data value that is above the threshold to be preserved and output. a mute command initiated by automute, master mute, individual i 2 c mute, the am interference mute sequence, or the bank switch mute sequence overrides an unmute command or a volume command. while a mute command is activated, the commanded channels transition to the mute state. when a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel. 1.9 output mixer the TAS5028A provides an 8 2 output mixer for channels 1, 2, 3, 4, 5, and 6. for channels 7 and 8 the TAS5028A provides an 8 3 output mixer. these mixers allow each output to be any ratio of any two (three) signal processed channels. the control parameters for the output crossbar mixer are programmable via the i 2 c interface.
introduction 21 sles112 ? june 2004 TAS5028A output gain coefficient 28 48 select output n gain coefficient 28 48 48 48 output gain coefficient 28 48 gain coefficient 28 48 48 48 gain coefficient 28 48 48 1, 2, 3, 4, 7 or 8 5 or 6 select output n select output n select output n select output n figure 1 ? 16. output mixers 1.10 pwm the TAS5028A has eight channels of high performance digital pwm modulators that are designed to drive switching output stages (backends) in both single-ended (se) and h-bridge (bridge tied load) configuration. the TAS5028A device uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. the TAS5028A uses an ad1 pwm modulation combined with a 5 th order noise shaper to provide a 102-db snr from 20 to 20 khz. the pwm section accepts 32-bit pcm data from the dap and outputs eight pwm audio output channels configurable as either: ? six channels to drive power stages + two channels to drive a differential input active filter to provide a separately controllable stereo line out ? eight channels to drive power stages the TAS5028A pwm section output supports both single-ended and bridge-tied loads. the pwm section provides a headphone pwm output to drive an external differential amplifier like the tpa112. the headphone circuit uses the pwm modulator for channels 1 and 2. the headphone will not operate while the six or eight backend drive channels are operating. the headphone will be enabled via a headphone select terminal or i 2 c command. the pwm section has individual channel dc blocking filters that can be enabled and disabled. the filter cutoff frequency is less than 1 hz. the pwm section has individual channel de-emphasis filters for 32, 44.1, and 48 khz that can be enabled and disabled.
introduction 22 sles112 ? june 2004 TAS5028A the interpolator, noise shaper, and pwm sections provide a pwm output with the following features: ? up to 8 oversampling. ? 8 at f s = 32 khz, 38 khz, 44.1 khz, 48 khz ? 4 at f s = 88.2 khz, 96 khz ? 2 at f s = 176.4 khz, 192 khz ? 5th order noise shaping ? 100-db dynamic range 0 ? 20 khz (TAS5028A + tas5111 system measured at speaker terminals) ? thd < 0.01% ? adjustable maximum modulation limit of 93.8% to 99.2% ? 3.3-v digital signal 1.10.1 dc blocking (high-pass enable / disable) each input channel incorporates a first order digital high-pass filter to block potential dc components. the filter ?3 db point is approximately 0.89-hz at 44.1-khz sampling rate. the high-pass filter can be enabled and disabled via the i 2 c interface. 1.10.2 de-emphasis filter for audio sources that have been pre-emphasized, a precision 50 s/15 s de-emphasis filter is provided to support the sampling rates of 32 khz, 44.1 khz, and 48 khz. figure 1 ? 17 shows a graph of the de-emphasis filtering characteristics. de-emphasis is set using two bits in the system control register. response ? db ? 10 0 frequency ? khz 3.18 (50 s) 10.6 (15 s) figure 1 ? 17. de-emphasis filter characteristics 1.10.3 am interference avoidance digital amplifiers can degrade am reception as a result of their rf emissions. texas instruments? patented am interference avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. during am reception, the TAS5028A adjusts the radiated emissions to provide an emission clear zone for the tuned am frequency. the inputs to the TAS5028A for this operation are the tuned am frequency, the if frequency, and the sample rate. the sample rate is automatically detected.
introduction 23 sles112 ? june 2004 TAS5028A tas5508a tas5508a analog receiver audio dsp adc pcm1802 tas5111 tas5111 tas5111 tas5111 tas5111 tas5111 tas5111 tas5111 digital receiver audio dsp tas5111 tas5111 tas5111 tas5111 tas5111 tas5111 tas5111 tas5111 the digital receiver or the audio dsp provides the master and bit clocks audio dsp provides the master and bit clocks figure 1 ? 18. block diagrams of typical systems requiring TAS5028A automatic am interference avoidance circuit
TAS5028A controls and status 25 sles112 ? june 2004 TAS5028A 2 TAS5028A controls and status the TAS5028A provides control and status information from both the i 2 c registers and device pins. this section describes some of these controls and status functions. the i 2 c summary and detailed register descriptions are contained in sections at the end of this document. 2.1 i 2 c status registers the TAS5028A has two status registers that provide general device information. these are the general status register 0 (0x01) and the error status register (0x02). 2.1.1 general status register (0x01) ? device identification code ? clip indicator ? the TAS5028A has a clipping indicator. writing to the register clears the indicator. ? bank switching is busy 2.1.2 error status register (0x02) ? no internal errors (the valid signal is high) ? a clock error has occurred ? these are sticky bits that are cleared by writing to the register. ? lrclk error ? when the number of mclks per lrclk is incorrect ? sclk error ? when the number of sclks per lrclk is incorrect ? frame slip ? when the number of mclks per lrclk changes by more than 10 mclk cycles ? pll phase-lock error ? this error status register is normally used for system development only. 2.2 TAS5028A pin controls the TAS5028A provide a number of terminal controls to manage the device operation. these controls are: ? reset ? pdn ? bknd_err ? hp_sel ? mute 2.2.1 reset (reset ) the TAS5028A is placed in the reset mode by setting the reset terminal low or by the power up reset circuitry when power is applied. reset is an asynchronous control signal that restores the TAS5028A to the hard mute state (m). master volume is immediately set to full attenuation (there is no ramp down). reset initiates the device reset without an mclk input. as long as the reset terminal is held low, the device is in the reset state. during reset, all i 2 c and serial data bus operations are ignored. table 2 ? 1 shows the device output signals while reset is active. table 2 ? 1. device outputs during reset signal signal state valid low pwm p-outputs low (m-state) pwm m-outputs low (m-state) sda signal input (not driven)
TAS5028A controls and status 26 sles112 ? june 2004 TAS5028A because reset is an asynchronous signal, clicks and pops produced during the application (the leading edge) of reset cannot be avoided. however, the transition from the hard mute state (m) to the operational state is performed using a quiet start up sequence to minimize noise. this control uses the pwm reset and unmute sequence to shut down and start up the pwm. a detailed description of these sequences is contained in the pwm section. if a completely quiet reset or power down sequence is desired, mute should be applied before applying reset . the rising edge of the reset pulse begins device initialization before the transition to the operational mode. during device initialization, all controls are reset to their initial states. table 2 ? 2 shows the default control settings following a reset. table 2 ? 2. values set during reset control setting clock register not valid high pass disabled unmute from clock error hard unmute post dap detection automute enabled eight ch predap detection automute enabled de ? emphasis de-emphasis disabled channel configuration control configured for the default setting headphone configuration control configured for the default setting serial data interface format i 2 s 24 bit individual channel mute no channels are muted automute delay 5 ms automute threshold 1 < 8 bits automute threshold 2 same as automute threshold 1 modulation limit maximum modulation limit of 97.7% six (or eight ? low) channel configuration eight channels slew rate limit disengaged for all channels interchannel delay ? 32, 0, ?16, 16, ?24, 8, ?8, ? 24 shutdown pwm on error enabled volume and mute update rate volume ramp 85 ms treble and bass slew rate update every 1.31 ms bank switching manual bank selection is enabled auto bank switching map all channels use bank 1 input mixer coefficients input n ? > channel n, no attenuation output mixer coefficients channel n ? > output n, no attenuation subwoofer sum into ch1 and 2 (5508) gain of 0 ch1 and 2 sum in subwoofer (5508) gain of 0 bass and treble bypass gain of 1 bass and treble inline gain of 0 master volume mute individual channel volumes 0 db all bass and treble indexes 0x12 neutral treble filter sets filter set 3 bass filter sets filter set 3 am interference enable disabled am interference if 455 am interference select sequence 1 tuned freq and mode 0000 , bcd
TAS5028A controls and status 27 sles112 ? june 2004 TAS5028A after the initialization time, the TAS5028A starts the transition to the operational state with the master volume set at mute. because the t as5028a has an external crystal time base, following the release of reset, the t as5028a sets the mclk and data rates and perform the initialization sequences. the pwm outputs are held at a mute state until the master volume is set to a value other than mute via i 2 c. 2.2.2 power down (pdn ) theTAS5028A can be placed into the power down mode by holding the pdn terminal low. when power down mode is entered, both the pll and the oscillator are shut down. volume is immediately set to full attenuation (there is no ramp down). this control uses the pwm mute sequence that provides a low click and pop transition to the hard mute state (m). a detailed description of the pwm mute sequence is contained in the pwm section. power down is an asynchronous operation that does not require mclk to go into the power down state. to initiate the power-up sequence requires mclk to be operational and the TAS5028A to receive 5 mclks prior to the release of pdn . as long as the pdn terminal is held low the device is in the power down state with the pwm outputs in a hard mute (m) state. during power down, all i 2 c and serial data bus operations are ignored. table 2 ? 3 shows the device output signals while pdn is active. table 2 ? 3. device outputs during power down signal signal state valid low pwm p-outputs m-state = low pwm m-outputs m-state = low sda signal input following the application of pdn , the t as5028a does not perform a quiet shutdown to prevent clicks and pops produced during the application (the leading edge) of this command. the application of pdn immediately performs a pwm stop. a quiet stop sequence can be performed by first applying mute before pdn . when pdn is released, the system goes to the end state specified by mute and bknd_err pins and the i 2 c register settings. the crystal time base allows the TAS5028A to determine the clk rates. once these rates are determined, the TAS5028A unmutes the audio. 2.2.3 backend error (bknd_err ) backend error is used to provide error management for backend error conditions. backend error is a level sensitive signal. backend error can be initiated by bringing the bknd_err terminal low for a minimum 5 mclk cycles. when bknd_err is brought low, the pwm sets either six or eight channels into the pwm backend error state. this state is described in the pwm section. once the backend error sequence is initiated, a delay of 5 ms is performed before the system starts the output re ? initialization sequence. after the initialization time, the TAS5028A begins normal operation. backend error does not affect other pwm modulator operations the number of channels that are affected by the bknd_err signal is dependent upon the 6-channel configuration signal. if the i 2 c setting 6-channel configuration is false, the TAS5028A places all eight pwm outputs in the pwm backend error state, while not affecting any other internal settings or operations. if the i 2 c setting six configuration is true, the TAS5028A brings the pwm outputs 1 ? 6 to a backend error state, while not affecting any other internal settings or operations. table 2 ? 4 shows the device output signal states during backend error.
TAS5028A controls and status 28 sles112 ? june 2004 TAS5028A table 2 ? 4. device outputs during backend error signal signal state valid low pwm p-outputs m-state ? low pwm m-outputs m-state ? low hppwm p-outputs m-state ? low hppwm m-outputs m-state ? low sda signal input (not driven) 2.2.4 speaker / headphone selector (hp_sel ) the hp_sel terminal enables the headphone output or the speaker outputs. the headphone output receives the processed data output from dap and pwm channels 1 and 2. in 6-channel configuration this feature does not affect the two lineout channels. when low, the headphone output is enabled. in this mode the speaker outputs are disabled. when high, the speaker outputs are enabled and the headphone is disabled. changes in the pin logic level results in a state change sequence using soft mute to the hard mute (m) state for both speaker and headphone followed by a soft unmute. when hp_sel is low, the configuration of channels 1 and 2 are defined by the headphone configuration register. when hp_sel is high, the channel 1 and 2 configuration registers define the configuration of channels 1 and 2. 2.2.5 mute (mute ) the mute control provides a noiseless volume ramp to silence. releasing mute provides a noiseless ramp to previous volume. the tas55508 has both a master and individual channel mute commands. a terminal is also provided for the master mute. the low active master mute i 2 c register and the mute terminal are logically or ?ed together. if either is set to low, a mute on all channels is performed. the master mute command operates on all channels regardless on whether the system is in six or eight channel configuration. when mute is invoked, the pwm output stops switching and then goes to an idle state. the master mute terminal is used to support a variety of other operations in the TAS5028A, such as setting the inter-channel delay, the serial interface format, and the clock rates. a mute command by the master mute terminal, individual i 2 c mute, the am interference mute sequence, the bank switch mute sequence, or automute overrides an unmute command or a volume command. while a mute is active, the commanded channels will be placed in a mute state. when a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel. 2.3 device configuration controls the TAS5028A provides a number of system configuration controls that are set at initialization and following a reset. ? channel configuration ? headphone configuration ? audio system configurations ? recovery from clock error ? volume and mute update rate ? modulation index limit ? inter-channel delay ? master clock and data rate controls ? bank controls
TAS5028A controls and status 29 sles112 ? june 2004 TAS5028A 2.3.1 channel configuration registers in order for the t as5028a to have full control of the power stages, registers 0x05 to 0x0c must be programmed to reflect the proper power stage and how each one should be controlled. channel configuration registers consist of eight registers, one for each channel. the primary reason for using these registers is that different power stages require different handling during start up, mute/unmute, shutdown, and error recovery. the t as5028a must select the sequence that gives the best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up. this sequence depends on which power stage is present at the TAS5028A output. table 2 ? 5. description of the channel configuration registers (0x05 to 0x0c) bit description d7 enable/disable err or recovery sequence. in case the bknd_recovery pin is pulled low, this register determines if this channel is to follow the error recovery sequence or to continue with no interruption. d6 determines if the power stage needs the TAS5028A valid pin to go low to reset the power stage. some power stages can be reset by a combination of pwm signals. for these devices, it is recommended to set this bit low, since the valid pin is shared for po wer stages. this provides better control of each power stage. d5 determines if the power stage needs the t as5028a valid pin to go low to mute the power stage. some power stages can be muted by a combination of pwm signals. for these devices, it is recommended to set this bit low, since the valid pin is shared for po wer stages. this provides better control of each power stage. d4 inverts the pwm output. inverting the pwm output can be an advantage if the power stage input pin are opposite the t as5028a pwm pinout. this makes routing on the pcb easier. to keep the phase of the output the speaker terminals must also be inverted. d3 the power stage tas5182 has a special pwm input. to ensure that the TAS5028A has full control in all occasions, the pwm output must be remapped. d2 can be used to handle click and pop for some applications. d1 this bit is normally used together with d2. for some power stages, both pwm signals must be high to get the desired operation o f both speaker outputs to be low. this bit sets the pwm outputs high-high during mute. d0 not used table 2 ? 6 lists the optimal setting for each output stage configuration. note that the default value is applicable in all configurations except the tas5182 se/btl configuration. table 2 ? 6. recommended TAS5028A configurations for texas instruments power stages device error recovery configuration d7 d6 d5 d4 d3 d2 d1 d0 default res btl 1 1 1 0 0 0 0 0 res btl 1 1 1 0 0 0 0 0 tas5111 res se 1 1 1 0 0 0 0 0 tas5111 aut btl 0 1 1 0 0 0 0 0 aut se 0 1 1 0 0 0 0 0 res btl 1 1 0 0 0 0 0 0 tas5112 res se 1 1 0 0 0 0 0 0 tas5112 aut btl 0 1 0 0 0 0 0 0 aut se 0 1 0 0 0 0 0 0 tas5182 res btl 1 1 1 0 1 0 0 0 tas5182 res se 1 1 1 0 1 0 0 0 res: the output stage requires valid to go low to recover from a shutdown. aut: the power stage can auto recover from a shutdown. btl: bridge tied load configuration se: single-ended configuration 2.3.2 headphone configuration registers the headphone configuration controls are identical to the speaker configuration controls. the headphone configuration control settings are used in place of the speaker configuration control settings for channels 1 and 2 when the headphones are selected. in reality however, there is only one used configuration setting for headphones and that is the default setting.
TAS5028A controls and status 30 sles112 ? june 2004 TAS5028A 2.3.3 audio system configurations the TAS5028A can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system and 8-channel system. the audio system configuration is set in the general control register (0xe0). bits d31 ? d2 must be zero and d0 is don?t care. d1 sets number of speakers in the system, including possible line outputs d1 must be configured as the following according to the audio system in the application: table 2 ? 7. audio system configuration (general control register 0xe0) audio system d31 ? d2 d1 d0 default 0 0 x 6 channel or 5.1 0 1 x 8 channel or 7.1 0 0 x 2.3.3.1 using line outputs in 6-channel configurations the audio system can be configured for a 6-channel configuration (with 2 line outs) by writing a 1 to bit d1 of register 0xe0 (general control register). in this configuration, channel 5 and 6 processing are exactly the same as the other channels, except that master volume has no effect. note that in 6-channel configuration, channels 5 and 6 are unaffected by backend error (bknd_err goes low). to use channels 5 and 6 as dry unprocessed line outs, the following setup is recommended: ? channel 5 volume and channel 6 volume should be set for a constant output such as 0 db. ? bass and treble for channels 5 and 6 can be used if desired. ? if a down mix is desired on the channel 5 and 6 as line out, the down mixing can be performed using the channel 5 and channel 6 input mixers. 2.3.4 recovery from clock error the TAS5028A can be set to either perform a volume ramp up during the recovery sequence of a clock error or to simply come up in the last state (or desired state if a volume or tone update was in progress). this feature is enabled via i 2 c system control register 0x03.
TAS5028A controls and status 31 sles112 ? june 2004 TAS5028A 2.3.5 volume and mute update rate the TAS5028A has fixed soft volume and mute ramp durations. the ramps are linear. the soft volume and mute ramp rates are adjustable by programming the i 2 c register 0xd0 for the appropriate number of steps to be 512, 1024, or 2048. the update is performed at a fixed rate regardless of the sample rate. ? in normal speed, the update rate is 1 step every 4 / fs seconds. ? in double speed, the update is 1 step every 8 / fs seconds. ? in quad speed, the update is 1 step every 16 / fs seconds. because of processor loading, the update rate can increase for some increments by +1/fs to +3/fs. however, the variance of the total time to go from +18 db to mute is less than 25%. table 2 ? 8. volume ramp rates in ms number of steps sample rate (khz) number of steps 44.1, 88.2, 176.4 32, 48, 96, 192 512 46.44 ms 42.67 ms 1024 92.88 ms 85.33 ms 2048 185.76 ms 170.67 ms 2.3.6 modulation index limit pwm modulation is a linear function of the audio signal. when the audio signal is 0, the pwm modulation is 50%. when the audio signal increases towards full scale, the pwm modulation increases towards 100%. for negative signals, the pwm modulations fall below 50% towards 0%. however, there is a limit to the maximum modulation possible. during the off-time period, the power stage connected to the TAS5028A output needs to get ready for he next on-time period. the maximum possible modulation is then set by the power stage requirements. all texas instruments power stages need maximum modulation to be 97.7%. this is also the default setting of the TAS5028A. default settings can be changed in the modulation index register (0x16). note that no change should be made to this register when using texas instruments power stages. 2.3.7 inter-channel delay an 8-bit value can be programmed to each of the eight pwm inter-channel delay registers to add a delay per channel from 0 to 255 clock cycles. the delays correspond to cycles of the high-speed internal clock, dclk. the default values are shown in table 2 ? 9. table 2 ? 9. interchannel delay default values i 2 c sub-address channel interchannel delay default (dclk periods) 0x1b 1 ? 24 0x1c 2 0 0x1d 3 ? 16 0x1e 4 +16 0x1f 5 ? 24 0x20 6 +8 0x21 7 ? 8 0x22 8 +24
TAS5028A controls and status 32 sles112 ? june 2004 TAS5028A this delay is generated in the pwm and can be changed at any time through the serial control interface i 2 c registers 0x1b ? 0x22. the absolute offset for channel 1 is set in i 2 c sub-address 0x23. note: if used correctly, setting the pwm channel delay can optimize the performance of a pure path digital amplifier system. the setting is based upon the type of backend power device that is used and the layout. these values are set during initialization using the i 2 c serial interface. unless otherwise noted, use the default values given in table 2 ? 9. 2.4 master clock and serial data rate controls the TAS5028A function only as a receiver of the mclk (master clock), sclk (shift clock), and lrclk (left/right clock) signals that controls the flow of data on the four serial data interfaces. the 13.5-mhz external crystal allows the TAS5028A to automatically detect mclk and the data rate. the mclk frequency can be 64 x fs, 128 x fs, 196 x fs, 256 x fs, 384 x fs, 512 x fs, or 768 x fs. the TAS5028A operates with the serial data interface signals lrclk and sclk synchronized to mclk. however, there is no constraint as to the phase relationship of these signals. the TAS5028A accepts a 64 x fs sclk rate and a 1 x fs lrclk. if the phase of sclk or lrclk drifts more than 10 mclk cycles since the last reset, the TAS5028A performs a clock error and resynchronize the clock timing. the clock and serial data interface have several control parameters: ? mclk ratio 64 fs, 128 fs, 196 fs, 256 fs, 384 fs, 512 fs, or 768 fs) ? i 2 c parameter ? data rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 khz ? i 2 c parameter ? am mode enable / disable ? i 2 c parameter during am interference avoidance, the clock control circuitry utilizes three other configuration inputs: ? tuned am frequency (for am interference avoidance) (550 ? 1750 khz) ? i 2 c parameter ? frequency set select (1 ? 4) ? i 2 c parameter ? sample rate ? i 2 c parameter or auto detected 2.4.1 pll operation the TAS5028A uses two internal clocks generated by two internal phase-locked loops (plls), the digital pll (dpll) and the analog pll (apll). the analog pll provides the reference clock for the pwm. the digital pll provides the reference clock for the digital audio processor and the control logic. the master clock mclk input provides the input reference clock for the apll. the external 13.5-mhz crystal provides the input reference clock for the digital pll. the crystal provides a time base to support a number of operations, including the detection of the mclk ratio, the data rate, and clock error conditions. the crystal time base provides a constant rate for all controls and signal timing. even if mclk is not present, the TAS5028A can receive and store i 2 c commands and provide status. 2.5 bank controls the TAS5028A permits the user to specify and assign sample rate dependent parameters for tone in one of three banks that can be manually selected or selected automatically based upon the data sample rate. each bank can be enabled for one or more specific sample rates via i 2 c bank control register 0x40. each bank set holds the following values: ? five bass filter-set selections (register 0xda) ? five treble filter-set selections (register 0xdc) the default selection for bank control is manual bank with bank 1 selected. note that if bank switching is used, bank 2 and bank 3 must be programmed on power ? up since the default values are all zeroes. if bank switching is used and bank 2 and bank 3 are not programmed correctly, then the output of the t as5028a could be muted when switching to those banks.
TAS5028A controls and status 33 sles112 ? june 2004 TAS5028A 2.5.1 manual bank selection the three bank selection bits of the bank control register allow the appropriate bank to be manually selected (000 = bank 1, 001 = bank 2, 010 = bank 3). in the manual mode, when a write occurs to the bass or treble coefficients, the current selected bank is updated. if audio data is streaming to the t as5028a, during a manual bank selection, the TAS5028A first performs a mute sequence, then performs the bank switch, and finally restores the volume using an unmute sequence. a mute command initiated by the bank switch mute sequence overrides an un ? mute command or a volume command. while a mute is active, the commanded channels are muted. when a channel is unmated, the volume level goes to the last commanded volume setting that has been received for that channel. if mclk or sclk is stopped, the TAS5028A performs a bank switch operation. if the clocks should start up once the manual bank switch command has been received, the bank switch operation is performed during the 5-ms silent start sequence. 2.5.2 automatic bank selection to enable automatic bank selection, a value of 3 is written into in the bank selection bits of the bank control register. banks are associated with one or more sample rates by writing values into the bank 1 or bank 2 data rate selection registers. the automatic base selection is performed when a frequency change is detected according to the following scheme: 1. the system scans bank 1 data rate associations to see if the bank 1 is assigned for that data rate. 2. if bank 1 is assigned, then the bank 1 coefficients will be loaded. 3. if it is not then, the system scans the bank 2 to see if bank 1 is assigned for that data rate. 4. if bank 2 is assigned, then the bank 2 coefficients will be loaded. 5. if it is not then, the system loads the bank 3 coefficients. the default is that all frequencies are enabled for bank 1. this default is expressed as a value of all 1s in the bank 1 auto-selection byte and all 0s in the bank 2 auto ? section byte. 2.5.2.1 coefficients write operations while automatic bank switch is enabled in automatic mode if a write occurs to the tone coefficient, the bank that is written to is the current bank. 2.5.3 bank set bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic switching modes without causing a bank switch to occur. bank set mode does not alter the current bank register mapping. it simply enables any bank?s coefficients to be updated while inhibiting any bank switches from taking place. in manual mode, this enables the coef ficients to be set without switching banks. in automatic mode this prevents a clock error or data rate change from corrupting a bank coefficient write. to update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the bank control register. this enables the tone coefficient values of bank 1, 2, or 3 to be respectively updated. once the coefficients of the bank have been updated, the bank selection bits are then returned to the desired manual or automatic bank selection mode. 2.5.4 bank switch timeline after a bank switch is initiated (manual or automatic), no i 2 c writes to the TAS5028A should occur before a minimum of 186 ms. this value is determined by the volume ramp rates for a particular sample rate. 2.5.5 bank switching example 1 problem: the audio unit containing a TAS5028A needs to handle different audio formats with dif ferent sample rates. format #1 requires fs = 32 khz, format #2 requires fs = 44.1 khz, and format #3 requires fs = 48 khz. the sample-rate dependent parameters in the TAS5028A require different coefficients and data depending on the sample rate.
TAS5028A controls and status 34 sles112 ? june 2004 TAS5028A strategy: use the TAS5028A bank switching feature to allow for managing and switching three banks associated with the three sample rates, 32 khz (bank 1), 44.1 khz (bank 2), and 48 khz (bank 3). one possible algorithm is to generate, load, and automatically manage bank switching for this problem: ? generate bank-related coef ficients (see above) for sample rates 32 khz, 44.1 khz, and 48 khz and include the same in the micro-based TAS5028A i 2 c firmware. ? on TAS5028A power up or reset, the micro runs the following TAS5028A initialization code: ? update bank 1 (write 0x00048040 to register 0x40). ? write bank-related i 2 c registers with appropriate values for bank 1. ? write bank 2 (write 0x00058040 to register 0x40). ? load bank-related i 2 c registers with appropriate values for bank 2. ? write bank 3 (write 0x00068040 to register 0x40). ? load bank-related i 2 c registers with appropriate values for bank 3. ? select automatic bank switching (write 0x00038040 to register 0x40) ? now when the audio media changes, the t as5028a automatically detects the incoming sample rate and automatically switches to the appropriate bank. in this example any sample rates other then 32 khz and 44.1 khz will use bank 3. if other sample rates are used, then the banks need to be set up differently. 2.5.6 bank switching example 2 problem: the audio system uses all of the sample rates supported by the TAS5028A. how can the automatic bank switching be set up to handle this situation? strategy: use the TAS5028A bank switching feature to allow for managing and switching three banks associated with sample rates as follows: ? bank 1: coefficients for 32 khz, 38 khz, 44.1 khz, and 48 khz ? bank 2: coefficients for 88.2khz and 96 khz ? bank 3: coefficients for 176.4 khz and 192 khz one possible algorithm is to generate, load, and automatically manage bank switching for this problem: ? generate bank-related coefficients for sample rates 48 khz (bank 1), 96 khz (bank 2), and 192 khz (bank 3) and include the same in the micro-based TAS5028A i 2 c firmware. ? on TAS5028A power ? up or reset, the micro runs the following TAS5028A initialization code: ? update bank 1 (write 0x0004f00c to register 0x40). ? write bank-related i 2 c registers with appropriate values for bank 1. ? write bank 2 (write 0x0005f00c to register 0x40). ? load bank-related i 2 c registers with appropriate values for bank 2. ? write bank 3 (write 0x0006f00c to register 0x40). ? load bank-related i 2 c registers with appropriate values for bank 3. ? select automatic bank switching (write 0x0003f00c to register 0x40) ? now when the audio media changes, the t as5028a automatically detects the incoming sample rate and automatically switches to the appropriate bank.
electrical specifications 35 sles120 ? september 2004 TAS5028A 3 electrical specifications 3.1 absolute maximum ratings units supply voltage, dvdd and dvd_pwm ?0.3 v to 3.6 v supply voltage, avdd_pll ?0.3 v to 3.6 v 3.3-v digital input ?0.5 v to dvdd + 0.5 v input voltage 5 v tolerant (2) digital input ?0.5 v to 6 v input voltage 1.8 v lvcmos (3) ?0.5 v to vref (1) + 0.5 v input clamp current, i ik (v i < 0 or v i > 1.8 v 20 ma output clamp current, i ok (v o < 0 or v o > 1.8 v) 20 ma operating free air temperature 0 c to 70 c storage temperature range, t stg ?65 c to 150 c ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only an d functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. vref is a 1.8-v supply derived from regulators internal to the TAS5028A chip. vref is on terminals vra_pll, vrd_pll, vr_dpll, vr_dig, and vr_pwm. these terminals are provided to permit use of external filter capacitors, but should not be used to source power to external devices. 2. 5-v tolerant inputs are reset , pdn , mute , hp_sel , sclk, lrclk, mclk, sdin1, sdin2, sdin3, sdin4, sda, and scl. 3. vra_pll, vrd_pll, vr_dpll, vr_dig, vr_pwm dissipation rating table (high-k board, 105 c junction) package t a 25 c power rating derating factor above t a = 25 c t a = 70 c power rating pag 1869 mw 23.36 mw/ c 818 mw 3.2 dynamic performance (at recommended operating conditions at 25 c) parameter test conditions min nom max units dynamic range TAS5028A + tas5111 a-weighted (fs = 48 khz) 102 db total harmonic distortion tas5111 a at 1 w 0.1% total harmonic distortion TAS5028A ouput 0.01% frequency response 32-khz to 96-khz sample rates 0.1 db frequency response 176.4, 192-khz sample rates 0.2 db 3.3 recommended operating conditions (over 0 c to 70 c) min nom max units digital supply voltage, dvdd and dvdd_pwm 3 3.3 3.6 v analog supply voltage, avdd_pll 3 3.3 3.6 v 3.3 v 2 high-level input voltage, v ih 5 ? v tolerant (4) 2 v high level input voltage, v ih 1.8 ? v lvcmos (xtl_in) 1.26 v 3.3 v 0.8 low-level input voltage, v il 5-v tolerant (4) 0.8 v low level input voltage, v il 1.8 ? v (xtl_in) 0.54 v operating ambient air temperature range, t a 0 25 70 c operating junction temperature range, t j 0 105 c note 4: 5-v tolerant inputs are sda, scl, reset , pdn , mute , hp_sel , sclk, lrclk, mclk, sdin1, sdin2, sdin3, and sdin4.
electrical specifications 36 sles120 ? september 2004 TAS5028A 3.4 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max units v high level output voltage 3.3 v ttl and 5 v (6) tolerant i oh = ?4 ma 2.4 v v oh high-level output voltage 1.8-v lvcmos (xtl_out) i oh = ?0.55 ma 1.44 v v low level output voltage 3.3-v ttl and 5 v (6) tolerant i ol = 4 ma 0.5 v v ol low-level output voltage 1.8-v lvcmos (xtl_out) i ol = 0.75 ma 0.5 v i oz high-impedance output current 3.3-v ttl 20 a 3.3-v ttl v i = v il 1 i il low-level input current 1.8-v lvcmos (xtl_in) v i = v il 1 a i il low level input current 5 v tolerant (5) v i = 0 v dvdd = 3 v 1 a 3.3-v ttl v i = v ih 1 i ih high-level input current 1.8-v lvcmos (xtl_in) v i = v ih 1 a i ih high level input current 5 v tolerant (5) v i = 5.5 v dvdd = 3 v 20 a fs = 48 khz 140 digital supply voltage dvdd fs = 96 khz 150 ma i input supply current digital supply voltage, dvdd fs = 192khz 155 ma i dd input supply current power down 8 analog supply voltage avdd normal 20 ma analog supply voltage, avdd power down 2 ma notes: 5. 5-v tolerant inputs are sda, scl, reset , pdn , mute , hp_sel , sclk, lrclk, mclk, sdin1, sdin2, sdin3, and sdin4. 6. 5-v tolerant outputs are scl and sda 3.5 pwm operation at recommended operating conditions over 0 c to 70 c parameter test conditions mode value units 32-khz data rate 4% 12 sample rate 384 khz output sample rate 1 ? 8 oversampled 44.1-, 88.2-, 176.4-khz data rate 4% 8 , 4 , and 2 sample rates 352.8 khz output sample rate 1 8 oversampled 48, 96, 192 khz data rate 4% 8 , 4 , and 2 sample rates 384 khz 3.6 switching characteristics 3.6.1 clock signals over recommended operating conditions (unless otherwise noted) 3.6.1.1 pll input parameters and external filter components parameter test conditions min typ max units f xtali frequency, xtal in only use 13.5-mhz crystal 1000 ppm 13.5 mhz f mclki frequency, mclk (1 / t cyc2 ) 2 50 mhz mclk duty cycle duty cycle 40% 50% 60% mclk minimum high time 2-v mclk = 49.152 mhz, within the min and max duty cycle constraints 5 ns mclk minimum low time 0.8-v mclk = 49.152 mhz, within the min and max duty cycle constraints 5 ns lrclk allowable drift before lrclk reset 10 mclks external pll filter cap c1 smd 0603 y5v 100 nf external pll filter cap c2 smd 0603 y5v 10 nf external pll filter resistor r smd 0603, metal film 200 ? external vra_pll decoupling smd, y5v 100 nf see the TAS5028A example application schematic in section 7.
electrical specifications 37 sles120 ? september 2004 TAS5028A 3.6.2 serial audio port 3.6.2.1 serial audio ports slave mode over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max units f sclkin frequency, sclk 64 fs c l = 30 pf 2.048 12.288 mhz t su1 setup time, lrclk to sclk rising edge 10 ns t h1 hold time, lrclk from sclk rising edge 10 ns t su2 setup time, sdin to sclk rising edge 10 ns t h2 hold time, sdin from sclk rising edge 10 ns lrclk frequency 32 48 192 khz sclk duty cycle 40% 50% 60% lrclk duty cycle 40% 50% 60% sclk rising edges between lrclk rising edges 64 64 sclk edges lrclk clock edge with respect to the falling edge of sclk ?1/4 1/4 sclk period t h1 t su1 t su2 t h2 sclk (input) lrclk (input) sdin1 sdin2 sdin3 figure 3 ? 1. slave mode serial data interface timing
electrical specifications 38 sles120 ? september 2004 TAS5028A 3.6.3 i 2 c serial control port operation 3.6.3.1 timing characteristics for i 2 c interface signals over recommended operating conditions (unless otherwise noted) parameter test conditions min max units f scl frequency, scl no wait states 400 khz t w(h) pulse duration, scl high 0.6 s t w(l) pulse duration, scl low 1.3 s t r rise time, scl and sda 300 ns t f fall time, scl and sda 300 ns t su1 setup time, sda to scl 100 ns t h1 hold time, scl to sda 0 ns t (buf) bus free time between stop and start condition 1.3 s t su2 setup time, scl to start condition 0.6 s t h2 hold time, start condition to scl 0.6 s t su3 setup time, scl to stop condition 0.6 s c l load capacitance for each bus line 400 pf scl sda t w(h) t w(l) t r t f t su1 t h1 figure 3 ? 2. scl and sda timing scl sda t h2 t (buf) t su2 t su3 start condition stop condition figure 3 ? 3. start and stop conditions timing
electrical specifications 39 sles120 ? september 2004 TAS5028A 3.6.4 reset timing (reset ) 3.6.4.1 control signal parameters over recommended operating conditions (unless otherwise noted) parameter min typ max units t r(dmstate) time to m-state low 370 ns t w(reset) pulse duration, reset active 400 none ns t r(i2c_ready) time to enable i 2 c 3 ms t r(run) device startup time 10 ms t w(reset) earliest time that m-state could be exited reset m-state t r(dmstate) = ~ < 300 ns t r(i2c_ready) start system t r(run) determine sclk rate and mclk ratio enable i 2 c figure 3 ? 4. reset timing since a crystal time base is used, the system determines the clk rates. once the data rate and master clock ratio is determined, the system outputs audio if a master volume command is issued. 3.6.5 power-down (pdn ) timing 3.6.5.1 control signal parameters over recommended operating conditions (unless otherwise noted) parameter min typ max units t p(dmstate) time to m-state low 300 s number of mclks preceding the release of pdn 5 t su device startup time 120 ms pdn m-state t su t p(dmstate) = ~ < 300 s figure 3 ? 5. power-down timing
electrical specifications 40 sles120 ? september 2004 TAS5028A 3.6.6 backend error (bknd_err ) 3.6.6.1 control signal parameters over recommended operating conditions (unless otherwise noted) parameter min typ max units t w(er) pulse duration, bknd_err active 350 none ns t p(valid_low) <100 s t p(valid_high) i 2 c programmable to be between 1 to 10 ms ?25 25 % of interval err_rcvry t p(valid_low) m-state t w(er) t p(valid_high) normal operation normal operation figure 3 ? 6. error recovery timing 3.6.7 mute timing?mute 3.6.7.1 control signal parameters over recommended operating conditions (unless otherwise noted) parameter min typ max units t d(vol volume ramp time defined by rate setting (1) ms note 1: see section 6.19. t d(vol) volume mute normal operation m-state normal operation t d(vol) figure 3 ? 7. mute timing
electrical specifications 41 sles120 ? september 2004 TAS5028A 3.6.8 headphone select (hp_sel ) 3.6.8.1 control signal parameters over recommended operating conditions (unless otherwise noted) parameter min max units t w(mute) pulse duration, hp_sel active 350 none ns t d(vol) soft volume update time defined by rate setting (2) ms t (sw) switch-over time 0.2 1 ms ms note 2: see section 6.19. t d(vol) hp volume hp_sel m-state t d(vol) spkr volume t (sw) t d(vol) spkr volume hp_sel m-state t d(vol) hp volume t (sw) (internal device state) figure 3 ? 8. hp_sel timing
serial audio interface control and timing 42 sles120 ? september 2004 TAS5028A 3.6.9 volume control 3.6.9.1 control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min max units maximum attenuation before mute individual volume, master volume or a combination of both ?127 db maximum gain individual volume, master volume 18 db maximum volume before the onset of clipping 0-db input, any modulation limit 0 db 3.7 serial audio interface control and timing 3.7.1 i 2 s timing i 2 s timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is low for the left channel and high for the right channel. a bit clock running at 64 fs is used to clock in the data. there is a delay of one bit clock from the time the lrclk signal changes state to the first bit of data on the data lines. the data is written msb first and is valid on the rising edge of bit clock. the TAS5028A masks unused trailing data bit positions. 23 22 sclk 32 clks lrclk (note reversed phase) left channel 24-bit mode 9 8 5 4 1 0 19 18 20-bit mode 5 4 1 0 16-bit mode 1 0 15 14 msb lsb 23 22 sclk 32 clks right channel 9 8 5 4 1 0 19 18 5 4 1 0 1 0 15 14 msb lsb 2-channel i 2 s (philips format) stereo input note: all data presented in 2s complement form with msb first. figure 3 ? 9. i 2 s format 64 ? fs format
serial audio interface control and timing 43 sles120 ? september 2004 TAS5028A 3.7.2 left justified left justified (lj) timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is high for the left channel and low for the right channel. a bit clock running at 64 fs is used to clock in the data. the first bit of data appears on the data lines at the same time the lrclk toggles. the data is written msb first and is valid on the rising edge of bit clock. the TAS5028A masks unused trailing data bit positions. 23 22 sclk 32 clks lrclk left channel 24-bit mode 9 8 5 4 1 0 msb lsb 23 22 32 clks lrclk right channel 9 8 5 4 1 0 msb lsb note: all data presented in 2s complement form with msb first. 18 20-bit mode 5 4 1 0 19 14 16-bit mode 1 0 15 18 5 4 1 0 19 14 1 0 15 2-channel left-justified stereo input figure 3 ? 10. left ? justified 64 ? fs format
serial audio interface control and timing 44 sles120 ? september 2004 TAS5028A 3.7.3 right justified right justified (rj) timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is high for the left channel and low for the right channel. a bit clock running at 64 fs is used to clock in the data. the first bit of data appears on the data 8-bit clock periods (for 24-bit data) after lrclk toggles. in rj mode the lsb of data is always clocked by the last bit clock before l/rclk transitions. the data is written msb first and is valid on the rising edge of bit clock. the TAS5028A masks unused leading data bit positions. 23 22 sclk 32 clks lrclk left channel 24-bit mode 19 18 15 14 1 0 19 18 20-bit mode 15 14 1 0 16-bit mode 1 0 15 14 msb lsb 2-channel right-justified (sony format) stereo input 23 22 32 clks right channel 19 18 15 14 1 0 19 18 15 14 1 0 1 0 15 14 msb lsb note: all data presented in 2s complement form with msb first. figure 3 ? 11. right ? justified 64 ? fs format
i 2 c serial control interface (slave address 0x36) 45 sles120 ? september 2004 TAS5028A 4i 2 c serial control interface (slave address 0x36) the TAS5028A has a bidirectional i 2 c interface that compatible with the i 2 c (inter ic) bus protocol and supports both 100 kbps and 400 kbps data transfer rates for single ? and multiple ? write and read operations. this is a slave only device that does not support a multi-master bus environment or wait state insertion. the control interface is used to program the registers of the device and to read device status. the TAS5028A supports the standard-mode i 2 c bus operation (100 khz maximum) and the fast i 2 c bus operation (400 khz maximum). the TAS5028A performs all i 2 c operations without i 2 c wait cycles. 4.1 general i 2 c operation the i 2 c bus employs two signals; sda (data) and scl (clock), to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. the address and data can be transferred in byte (8 bit) format, with the most significant bit (msb) transferred first. in addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the data terminal (sda) while the clock is high to indicate a start and stop conditions. a high-to-low transition on sda indicates a start and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock period. these conditions are shown in figure 4 ? 1. the master generates the 7-bit slave address and the read/write (r/w) bit to open communication with another device and then wait for an acknowledge condition. the TAS5028A holds sda low during acknowledge clock period to indicate an acknowledgement. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7-bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. an external pullup resistor must be used for the sda and scl signals to set the high level for the bus. 7 bit slave address r/ w 8 bit register address (n) a 8 bit register data for address (n) start stop sda scl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a 7 6 5 4 3 2 1 0 8 bit register data for address (n) 7 6 5 4 3 2 1 0 aa figure 4 ? 1. typical i 2 c sequence there is no limit on the number of bytes that can be transmitted between start and stop conditions. when the last word trans fers, the master generates a stop condition to release the bus. a generic data transfer sequence is shown in figure 4 ? 1. the 7-bit address for the TAS5028A is 0011011. 4.2 single ? and multiple ? byte transfers the serial control interface supports both single ? byte and multiple ? byte read/write operations for status registers and the general control registers associated with the pwm. however, for the dap data processing registers, the serial control interface supports only multiple ? byte (4 bytes) read/write operations. during multiple ? byte read operations, the TAS5028A responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. if a particular subaddress does not contain 32 bits, the unused bits are read as logic 0. during multiple ? byte write operations, the TAS5028A compares the number of bytes transmitted to the number of bytes that are required for each specific sub address. if a write command is received for a mixer coefficient, the TAS5028A expects to receive one 32-bit word. if fewer than 32 bits are required when a stop command (or another start command) is received, the data received is discarded.
i 2 c serial control interface (slave address 0x36) 46 sles120 ? september 2004 TAS5028A supplying a subaddress for each subaddress transaction is referred to as random i 2 c addressing. the TAS5028A also supports sequential i 2 c addressing. for write transactions, if a subaddress is issued followed by data for that subaddress and the fifteen subaddresses that follow, a sequential i 2 c write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5028A. for i 2 c sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. as was true for random addressing, sequential addressing requires that a complete set of data be transmitted. if only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. however, all other data written is accepted; just the incomplete data is discarded. 4.3 single ? byte write as shown in figure 4 ? 2, a single ? byte data write transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. the read/write bit determines the direction of the data transfer. for a write data transfer, the read/write bit will be a 0. after receiving the correct i 2 c device address and the read/write bit, the TAS5028A device responds with an acknowledge bit. next, the master transmits the address byte or bytes corresponding to the TAS5028A internal memory address being accessed. after receiving the address byte, the TAS5028A again responds with an acknowledge bit. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the TAS5028A again responds with an acknowledge bit. finally, the master device transmits a stop condition to complete the single ? byte data ? write transfer. a6 a5 a4 a3 a2 a1 a0 r/w ack a7 a6 a5 a4 a3 a2 a1 a0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack start condition stop condition acknowledge acknowledge acknowledge i 2 c device address and read/write bit sub-address data byte figure 4 ? 2. single ? byte write transfer 4.4 multiple ? byte write a multiple ? byte data write transfer is identical to a single ? byte data write transfer except that multiple data bytes are transmitted by the master device to TAS5028A as shown in figure 4 ? 3. after receiving each data byte, the TAS5028A responds with an acknowledge bit. d7 d0 ack stop condition acknowledge i 2 c device address and read/write bit sub-address last data byte a6 a5 a1 a0 r/w ack a7 a5 a1 a0 ack d7 ack start condition acknowledge acknowledge acknowledge first data byte a4 a3 a6 other data bytes ack acknowledge d0 d7 d0 figure 4 ? 3. multiple ? byte write transfer 4.5 incremental multiple ? byte write the i 2 c supports a special mode which permits i 2 c write operations to be broken up into multiple data write operations that are multiples of 4 data bytes. these are 6 ? byte, 10 ? byte, 14 ? byte, 18 ? byte, ... etc., write operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data. this permits the system to incrementally write large register values without blocking other i 2 c transactions. this feature is enabled by the append subaddress function in the TAS5028A. this function enables the TAS5028A to append 4 bytes of data to a register that was opened by a previous i 2 c register write operation but has not received its complete number of data bytes. because the length of the long registers is a multiple of 4 bytes, using 4-byte transfers has only an integer number of append operations.
i 2 c serial control interface (slave address 0x36) 47 sles120 ? september 2004 TAS5028A when the correct number of bytes has been received, the TAS5028A starts processing the data. the procedure to perform an incremental multibyte ? write operation is as follows: 1. start a normal i 2 c write operation by sending the device address, write bit, register subaddress, and the first four bytes of the data to be written. at the end of that sequence, send a stop condition. at this point, the register has been opened and accepts the remaining data that is sent by writing 4 ? byte blocks of data to the append subaddress (0xfe). 2. at a later time, one or more append data transfers are performed to incrementally transfer the remaining number of bytes in sequential order to complete the register write operation. each of these append operations will be composed of the device address, write bit, append subaddress (0xfe), and four bytes of data followed by a stop condition. 3. the operation will be terminated due to an error condition and the data will be flushed: a. if a new subaddress is written to the t as5028a before the correct number of bytes have been written. b. if more or fewer than 4 bytes are data written at the beginning or during any of the append operations. c. if a read bit is sent. 4.6 single ? byte read as shown in figure 4 ? 4, a single ? byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. for the data read transfer, both a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the read/write bit will be a 0. after receiving the TAS5028A address and the read/write bit, the t as5028a responds with an acknowledge bit. in addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the t as5028a address and the read/write bit again. this time the read/write bit will be a 1, indicating a read transfer. after receiving the t as5028a and the read/write bit the t as5028a again responds with an acknowledge bit. next, the TAS5028A transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single ? byte data ? read transfer. a6 a5 a0 r/w ack a7 a6 a5 a4 a0 ack a6 a5 a0 ack start condition stop condition acknowledge acknowledge acknowledge i 2 c device address and read/write bit sub-address data byte d7 d6 d1 d0 ack i 2 c device address and read/write bit not acknowledge r/w a1 a1 repeat start condition figure 4 ? 4. single ? byte read transfer 4.7 multiple ? byte read a multiple ? byte data ? read transfer is identical to a single ? byte data read transfer except that multiple data bytes are transmitted by the TAS5028A to the master device as shown in figure 4 ? 5. except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. a6 a0 ack acknowledge i 2 c device address and read/write bit r/w a6 a0 r/w ack a0 ack d7 d0 ack start condition stop condition acknowledge acknowledge acknowledge last data byte ack first data byte repeat start condition not acknowledge i 2 c device address and read/write bit sub-address other data bytes a7 a6 a5 d7 d0 ack acknowledge d7 d0 figure 4 ? 5. multiple byte read transfer
serial control i 2 c register summary 49 sles112 ? june 2004 TAS5028A 5 serial control i 2 c register summary the TAS5028A slave address is 0x36. see the serial control i 2 c register bit definitions chapter for complete bit definitions. note that u indicates unused bits. i 2 c subaddress total bytes register fields description of contents default state 0x00 1 clock control register set data rate and mclk frequency 1. fs = 48 khz 2. mclk = 256 fs = 12.288 mhz 0x01 1 general status register clip indicator and id code for the TAS5028A 0x01 0x02 1 error status register pll, sclk, lrclk, and frame slip errors no errors 0x03 1 system control register 1 pwm high pass, clock set, un-mute select 1. pwm high pass disabled 2. auto clock set 3. hard un-mute on clock error recovery 0x04 1 system control register 2 automute and de-emphasis control 1. automute timeout disable 2. post-dap detection automute enabled 3. 8-ch device input detection automute enabled 4. un-mute threshold 6 db over input 5. no de-emphasis 0x05?0x0c 1 channel configuration registers configure channels 1, 2, 3, 4, 5, 6, 7, and 8 1. enable backend reset 2. valid low for reset 3. valid low for mute 4. normal bepolarity 5. don?t remap the output for the tas5182 6. don?t go low-low in mute 7. don?t remap hi-z state to low-low state 0x0d 1 headphone configuration register configure headphone output 1. disable backend reset sequence 2 valid does not have to be low for reset 3. valid does not have to be low for mute 4. normal bepolarity 5. do not remap output to comply with 5182 6. do not go low-low in mute 7. do not remap hi ? z state to low-low state 0x0e 1 serial data interface register set serial data interface to right justified, i2s, or left justified 24-bit i2s 0x0f 1 soft mute register soft mute for channels 1, 2, 3, 4, 5, 6, 7, and 8 un-mute all channels 0x10?0x13 reserved 0x14 1 automute control set auto-mute delay and threshold 1. set auto-mute delay = 5 ms 2. set auto-mute threshold less than bit 8 0x15 1 automute pwm threshold and backend reset period set pwm auto-mute threshold, set backend reset period 1. set the pwm threshold the same as the TAS5028A input threshold 2. set backend reset period = 5 ms 0x16 1 modulation limit register set modulation index 97.7% 0x17?0x1a reserved
serial control i 2 c register summary 50 sles112 ? june 2004 TAS5028A i 2 c subaddress default state description of contents register fields total bytes 0x1b?0x22 1/reg. interchannel delay registers set inter-channel delay channel 1 delay = ?23 dclk periods channel 2 delay = 0 dclk periods channel 3 delay = ?16 dclk periods channel 4 delay = 16 dclk periods channel 5 delay = ?24 dclk periods channel 6 delay = 8 dclk periods channel 7 delay = ?8 dclk periods channel 8 delay = 24 dclk periods 0x23 1 inter-channel offset absolute delay offset for channel 1 (0 ? 255) minimum absolute default = 0 dclk periods 0x24?0x3f reserved 0x40 4 bank switching command register set up dap coefficients bank switching for banks 1, 2, and 3 manual selection ? bank 1 0x41?0x48 32/reg see input mixer registers (0x41 ? 0x48, channels 1 ? 8) , section 6.15 8x8 input crossbar mixer setup sdin1 ? left to input mixer 1 sdin1 ? right to input mixer 2 sdin2 ? left to input mixer 3 sdin2 ? right to input mixer 4 sdin3 ? left to input mixer 5 sdin3 ? right to input mixer 6 sdin4 ? left to input mixer 7 sdin4 ? right to input mixer 8 0x49?0x88 reserved 0x89?0x90 8 bass and treble bypass ch 1?8 bypass bass and treble for channels 1?8 bass and treble bypassed for all channels 0x91?0xa9 reserved 0xaa 8 sel op1?8 and mix to s select 0 to 2 of eight channels to output mixer s select channel 1 to pwm 1 0xab 8 sel op1?8 and mix to t select 0 to 2 of eight channels to output mixer t select channel 2 to pwm 2 0xac 8 sel op1?8 and mix to u select 0 to 2 of eight channels to output mixer u select channel 3 to pwm 3 0xad 8 sel op1?8 and mix to v select 0 to 2 of eight channels to output mixer v select channel 4 to pwm 4 0xae 8 sel op1?8 and mix to w select 0 to 2 of eight channels to output mixer w select channel 5 to pwm 5 0xaf 8 sel op1?8 and mix to x select 0 to 2 of eight channels to output mixer x select channel 6 to pwm 6 0xb0 12 sel op1?8 and mix to y select 0 to 3 of eight channels to output mixer y select channel 7 to pwm 7 0xb1 12 sel op1?8 and mix to z select 0 to 3 of eight channels to output mixer z select channel 8 to pwm 8 0xb2?0xcf reserved 0xd0 4 vol, t and b slew rates u (31:24), u (23:16), u (15:12) vsr(11:8), tbsr(7:0) 0x00, 0x00, 0x01, 0x3f 0xd1 4 ch1 volume channel 1 volume 0 db 0xd2 4 ch2 volume channel 2 volume 0 db 0xd3 4 ch3 volume channel 3 volume 0 db 0xd4 4 ch4 volume channel 4 volume 0 db
serial control i 2 c register summary 51 sles112 ? june 2004 TAS5028A i 2 c subaddress default state description of contents register fields total bytes 0xd5 4 ch5 volume channel 5 volume 0 db 0xd6 4 ch6 volume channel 6 volume 0 db 0xd7 4 ch7 volume channel 7 volume 0 db 0xd8 4 ch8 volume channel 8 volume 0 db 0xd9 4 master volume master volume mute oxda 4 bass filter set (1?5) bass filter set (all channels) filter set 3 0xdb 4 bass filter index bass filter level (all channels) 0 db 0xdc 4 treble filter set (1?5) treble filter set (all channels) filter set 3 0xdd 4 treble filter index treble filter level (all channels) 0 db 0xde 4 am mode and tuned frequency register set-up am mode for am-interference reduction am mode disabled select sequence 1 if frequency = 455 khz use bcd-tuned frequency 0xdf reserved 0xe0 4 general control register six or eight channel configuration eight channel configuration 0xe1?0xfd reserved 0xfe 4 (min) multiple bit writer append register special register n/a 0xff reserved
serial control interface register definitions 53 sles120 ? september 2004 TAS5028A 6 serial control interface register definitions unless otherwise noted, the i 2 c register default values are in bold font. note that u indicates unused bits. 6.1 clock control register (0x00) bit d1 is don?t care . table 6 ? 1. clock control register d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 ? ? ? ? 32-khz data rate 0 0 1 ? ? ? ? 38-khz data rate 0 1 0 ? ? ? ? 44.1-khz data rate 0 1 1 ? ? ? ? 48-khz data rate 1 0 0 ? ? ? ? 88.2-khz data rate 1 0 1 ? ? ? ? 96-khz data rate 1 1 0 ? ? ? ? 176.4-khz data rate 1 1 1 ? ? ? ? 192-khz data rate ? ? ? 0 0 0 mclk frequency = 64 ? ? ? 0 0 1 mclk frequency = 128 ? ? ? 0 1 0 mclk frequency = 192 ? ? ? 0 1 1 mclk frequency = 256 ? ? ? 1 0 0 mclk frequency = 384 ? ? ? 1 0 1 mclk frequency = 512 ? ? ? 1 1 0 mclk frequency = 768 ? ? ? 1 1 1 reserved ? ? ? ? ? ? 1 clock register is valid (read only) ? ? ? ? ? ? 0 clock register is not valid (read only) 6.2 general status register 0 (0x01) table 6 ? 2. general status register (0x01) d7 d6 d5 d4 d3 d2 d1 d0 function 1 ? ? ? ? ? ? ? clip indicator ? 1 ? ? ? ? ? ? bank switching busy ? ? 0 0 0 0 0 1 identification code for TAS5028A 6.3 error status register (0x02) note that the error bits are sticky bits that are not cleared by the hardware. this means that the software must clear the register (write zeroes) and then read them to determine if there are any persistent errors. table 6 ? 3. error status register (0x02) d7 d6 d5 d4 d3 d2 d1 d0 function 1 ? ? ? ? ? ? ? pll phase lock error ? 1 ? ? ? ? ? ? pll auto lock error ? ? 1 ? ? ? ? ? sclk error ? ? ? 1 ? ? ? ? lrclk error ? ? ? ? 1 ? ? ? frame slip 0 0 0 0 0 0 0 0 no errors
serial control interface register definitions 54 sles120 ? september 2004 TAS5028A 6.4 system control register 1 (0x03) bit d5, d2, d1, and d0 are don?t care . table 6 ? 4. system control register 1 d7 d6 d5 d4 d3 d2 d1 d0 function 0 ? ? ? pwm high pass disabled 1 ? ? ? pwm high pass enabled ? ? 0 soft unmute on recovery from clock error ? ? 1 hard unmute on recovery from clock error 6.5 system control register 2 (0x04) bit d3 and d2 are don?t care . table 6 ? 5. system control register 2 d7 d6 d5 d4 d3 d2 d1 d0 function 0 ? ? ? ? ? reserved ? 0 ? ? ? ? pwm automute detection enabled ? 1 ? ? ? ? pwm automute detection disabled 0 ? ? ? 8 ch device input detection automute enabled ? ? 1 ? ? ? 8 ch device input detection automute disabled ? ? ? 0 ? ? unmute threshold 6 db over input threshold ? ? ? 1 ? ? unmute threshold equal to input threshold ? ? ? ? 0 0 no de-emphasis ? ? ? ? 0 1 de-emphasis for fs = 32 khz ? ? ? ? 1 0 de-emphasis for fs = 44.1 khz ? ? ? ? 1 1 de-emphasis for fs = 48 khz 6.6 channel configuration control register (0x05 ? x0c) channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, and 0x0c. bit d0 is don?t care . table 6 ? 6. channel configuration control registers d7 d6 d5 d4 d3 d2 d1 d0 function 0 ? ? ? ? ? ? disable backend reset sequence for a channel ? beerrorrecen 1 ? ? ? ? ? ? enable backend reset sequence for a channel ? 0 ? ? ? ? ? valid does not have to be low for this channel to be reset bevalidrst ? 1 ? ? ? ? ? valid must be low for this channel to be reset ? ? 0 ? ? ? ? valid does not have to be low for this channel to be muted bevalidmute ? ? 1 ? ? ? ? valid must be low for this channel to be muted ? ? ? 0 ? ? ? normal bepolarity ? ? ? 1 ? ? ? switches pwm+ and pwm? and invert audio signal ? ? ? ? 0 ? ? do not remap output to comply with 5182 interface ? ? ? ? 1 ? ? remap output to comply with 5182 interface ? ? ? ? ? 0 ? do not go to low low in mute ? belowmute ? ? ? ? ? 1 ? go to low-low in mute ? ? ? ? ? ? 0 do not remap hi-z state to low-low state ? be5111bsmute ? ? ? ? ? ? 1 remap hi-z state to low-low state
serial control interface register definitions 55 sles120 ? september 2004 TAS5028A 6.7 headphone configuration control register (0x0d) bit d0 is don?t care . table 6 ? 7. headphone configuration control register d7 d6 d5 d4 d3 d2 d1 d0 function 0 ? ? ? ? ? ? disable backend reset sequence for a channel ? beerrorrecen 1 ? ? ? ? ? ? enable backend reset sequence for a channel ? 0 ? ? ? ? ? valid does not have to be low for this channel to be reset bevalidrst ? 1 ? ? ? ? ? valid must be low for this channel to be reset ? ? 0 ? ? ? ? valid does not have to be low for this channel to be muted bevalidmute ? ? 1 ? ? ? ? valid must be low for this channel to be muted ? ? ? 0 ? ? ? normal bepolarity ? ? ? 1 ? ? ? switches pwm+ and pwm? and invert audio signal ? ? ? ? 0 ? ? do not remap output to comply with 5182 interface ? ? ? ? 1 ? ? remap output to comply with 5182 interface ? ? ? ? ? 0 ? do not go to low low in mute ? belowmute ? ? ? ? ? 1 ? go to low-low in mute ? ? ? ? ? ? 0 do not remap hi-z state to low-low state ? be5111bsmute ? ? ? ? ? ? 1 remap hi-z state to low-low state 6.8 serial data interface control register (0x0e) nine serial modes can be programmed i 2 c. table 6 ? 8. serial data interface control register format receive serial data interface format word lengths d7?d4 d3 d2 d1 d0 right justified 16 0000 0 0 0 0 right justified 20 0000 0 0 0 1 right justified 24 0000 0 0 1 0 i 2 s 16 0000 0 0 1 1 i 2 s 20 0000 0 1 0 0 i 2 s 24 0000 0 1 0 1 left justified 16 0000 0 1 1 0 left justified 20 0000 0 1 1 1 left justified 24 0000 1 0 0 0 illegal 0000 1 0 0 1 illegal 0000 1 0 1 0 illegal 0000 1 0 1 1 illegal 0000 1 1 0 0 illegal 0000 1 1 0 1 illegal 0000 1 1 1 0 illegal 0000 1 1 1 1
serial control interface register definitions 56 sles120 ? september 2004 TAS5028A 6.9 soft mute register (0x0f) table 6 ? 9. soft mute register d7 d6 d5 d4 d3 d2 d1 d0 function ? ? ? ? ? ? ? 1 soft ? mute channel 1 ? ? ? ? ? ? 1 ? soft ? mute channel 2 ? ? ? ? ? 1 ? ? soft ? mute channel 3 ? ? ? ? 1 ? ? ? soft ? mute channel 4 ? ? ? 1 ? ? ? ? soft ? mute channel 5 ? ? 1 ? ? ? ? ? soft ? mute channel 6 ? 1 ? ? ? ? ? ? soft ? mute channel 7 1 ? ? ? ? ? ? ? soft ? mute channel 8 0 0 0 0 0 0 0 0 unmute all channels 6.10 automute control register(0x14) table 6 ? 10. automute control register d7 d6 d5 d4 d3 d2 d1 d0 function ? ? ? ? 0 0 0 0 set input automute and pwm automute delay to 1 ms ? ? ? ? 0 0 0 1 set input automute and pwm automute delay to 2 ms ? ? ? ? 0 0 1 0 set input automute and pwm automute delay to 3 ms ? ? ? ? 0 0 1 1 set input automute and pwm automute delay to 4 ms ? ? ? ? 0 1 0 0 set input automute and pwm automute delay to 5 ms ? ? ? ? 0 1 0 1 set input automute and pwm automute delay to 10 ms ? ? ? ? 0 1 1 0 set input automute and pwm automute delay to 20 ms ? ? ? ? 0 1 1 1 set input automute and pwm automute delay to 30 ms ? ? ? ? 1 0 0 0 set input automute and pwm automute delay to 40 ms ? ? ? ? 1 0 0 1 set input automute and pwm automute delay to 50 ms ? ? ? ? 1 0 1 0 set input automute and pwm automute delay to 60 ms ? ? ? ? 1 0 1 1 set input automute and pwm automute delay to 70ms ? ? ? ? 1 1 0 0 set input automute and pwm automute delay to 80 ms ? ? ? ? 1 1 0 1 set input automute and pwm automute delay to 90 ms ? ? ? ? 1 1 1 0 set input automute and pwm automute delay to 100 ms ? ? ? ? 1 1 1 1 set input automute and pwm automute delay to 110 ms 0 0 0 0 ? ? ? set input automute threshold less than bit 1 (zero input si g nal), lowest automute 0 0 0 1 ? ? ? ? set input automute threshold less than bit 1 (zero input signal) , lowest automute threshold. 0 0 1 0 ? ? ? ? set input automute threshold less than bit 2 0 0 1 1 ? ? ? ? set input automute threshold less than bit 3 0 1 0 0 ? ? ? ? set input automute threshold less than bit 4 0 1 0 1 ? ? ? ? set input automute threshold less than bit 5 0 1 1 0 ? ? ? ? set input automute threshold less than bit 6 0 1 1 1 ? ? ? ? set input automute threshold less than bit 7 1 0 0 0 ? ? ? ? set input automute threshold less than bit 8 1 0 0 1 ? ? ? ? set input automute threshold less than bit 9 1 0 1 0 ? ? ? ? set input automute threshold less than bit 10 1 0 1 1 ? ? ? ? set input automute threshold less than bit 11 1 1 0 0 ? ? ? ? set input automute threshold less than bit 12 1 1 0 1 ? ? ? ? set input automute threshold less than bit 13 1 1 1 0 ? ? ? ? set input automute threshold less than bit 14 1 1 1 1 ? ? ? ? set input automute threshold less than bit 15
serial control interface register definitions 57 sles120 ? september 2004 TAS5028A 6.11 automute pwm threshold and backend reset period (0x15) table 6 ? 11. automute pwm threshold and backend reset period d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 ? ? ? ? set pwm automute threshold equals input automute threshold 0 0 0 1 ? ? ? ? set pwm automute threshold 1 bit more than input automute threshold 0 0 1 0 ? ? ? ? set pwm automute threshold 2 bits more than input automute threshold 0 0 1 1 ? ? ? ? set pwm automute threshold 3 bits more than input automute threshold 0 1 0 0 ? ? ? ? set pwm automute threshold 4 bits more than input automute threshold 0 1 0 1 ? ? ? ? set pwm automute threshold 5 bits more than input automute threshold 0 1 1 0 ? ? ? ? set pwm automute threshold 6 bits more than input automute threshold 0 1 1 1 ? ? ? ? set pwm automute threshold 7 bits more than input automute threshold 1 0 0 0 ? ? ? ? set pwm automute threshold equals input automute threshold 1 0 0 1 ? ? ? ? set pwm automute threshold 1 bit less than input automute threshold 1 0 1 0 ? ? ? ? set pwm automute threshold 2 bits less than input automute threshold 1 0 1 1 ? ? ? ? set pwm automute threshold 3 bits less than input automute threshold 1 1 0 0 ? ? ? ? set pwm automute threshold 4 bits less than input automute threshold 1 1 0 1 set pwm automute threshold 5 bits less than input automute threshold 1 1 1 0 set pwm automute threshold 6 bits less than input automute threshold 1 1 1 1 set pwm automute threshold 7 bits less than input automute threshold ? ? ? ? 0 0 0 0 set backend reset period < 1 ms ? ? ? ? 0 0 0 1 set backend reset period 1 ms ? ? ? ? 0 0 1 0 set backend reset period 2 ms ? ? ? ? 0 0 1 1 set backend reset period 3 ms ? ? ? ? 0 1 0 0 set backend reset period 4 ms ? ? ? ? 0 1 0 1 set backend reset period 5 ms ? ? ? ? 0 1 1 0 set backend reset period 6 ms ? ? ? ? 0 1 1 1 set backend reset period 7 ms ? ? ? ? 1 0 0 0 set backend reset period 8 ms ? ? ? ? 1 0 0 1 set backend reset period 9 ms ? ? ? ? 1 0 1 0 set backend reset period 10 ms ? ? ? ? 1 0 1 1 set backend reset period 10 ms ? ? ? ? 1 1 x x set backend reset period 10 ms 6.12 modulation index limit register (0x16) table 6 ? 12. modulation index limit register d7 d6 d5 d4 d3 d2 d1 d0 limit [dclks] min width [dclks] modulation index 0 0 0 1 2 99.2% 0 0 1 2 4 98.4% 0 1 0 3 6 97.7% 0 1 1 4 8 96.9% 1 0 0 5 10 96.1% 1 0 1 6 12 95.3% 1 1 0 7 14 94.5% 1 1 1 8 16 93.8%
serial control interface register definitions 58 sles120 ? september 2004 TAS5028A 6.13 interchannel channel delay registers (0x1b ? 0x22) and offset register (0x23) channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into (0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, and 0x22). bits d1 and d0 are don?t care . table 6 ? 13. interchannel channel delay registers d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 minimum absolute delay, 0 dclk cycles, default for channel 1 0 1 1 1 1 1 maximum positive delay, 31 4 dclk cycles 1 0 0 0 0 0 maximum negative delay, ?32 4 dclk cycles 1 0 0 0 0 0 default value for channel 1: ?32 0 0 0 0 0 0 default value for channel 2: 0 1 1 0 0 0 0 default value for channel 3: ?16 0 1 0 0 0 0 default value for channel 4: 16 1 0 1 0 0 0 default value for channel 5: ?24 0 0 1 0 0 0 default value for channel 6: 8 1 1 1 0 0 0 default value for channel 7: ?8 0 1 1 0 0 0 default value for channel 8: 24 the offset register is mapped into 0x23. table 6 ? 14. channel offset register d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 minimum absolute offset, 0 dclk cycles default for channel 1 1 1 1 1 1 1 1 1 maximum absolute delay, 255 dclk cycles
serial control interface register definitions 59 sles120 ? september 2004 TAS5028A 6.14 bank switching command (0x40) bits d31?d24, d22?d19 are don?t care . table 6 ? 15. bank switching command d31 d30 d29 d28 d27 d26 d25 d24 function unused bits d23 d22 d21 d20 d19 d18 d17 d16 function ? 0 0 0 manual selection bank 1 ? 0 0 1 manual selection bank 2 ? 0 1 0 manual selection bank 3 ? 0 1 1 automatic bank selection ? 1 0 0 update the values in bank 1 ? 1 0 1 update the values in bank 2 ? 1 1 0 update the values in bank 3 0 1 1 1 update only the bank map 0 x x x update the bank map using values in d15?d0 1 x x x do not update the bank map using values in d15?d0 d15 d14 d13 d12 d11 d10 d9 d8 function 1 ? ? ? ? ? ? ? 32-khz data rate ? use bank 1 ? 1 ? ? ? ? ? ? 38-khz data rate ? use bank 1 ? ? 1 ? ? ? ? ? 44.1-khz data rate ? use bank 1 ? ? ? 1 ? ? ? ? 48-khz data rate ? use bank 1 ? ? ? ? 1 ? ? ? 88.2-khz data rate ? use bank 1 ? ? ? ? ? 1 ? ? 96-khz data rate ? use bank 1 ? ? ? ? ? ? 1 ? 176.4-khz data rate ? use bank 1 ? ? ? ? ? ? ? 1 192-khz data rate ? use bank 1 1 1 1 1 1 1 1 1 default d7 d6 d5 d4 d3 d2 d1 d0 function 1 ? ? ? ? ? ? ? 32-khz data rate ? use bank 2 ? 1 ? ? ? ? ? ? 38-khz data rate ? use bank 2 ? ? 1 ? ? ? ? ? 44.1-khz data rate ? use bank 2 ? ? ? 1 ? ? ? ? 48-khz data rate ? use bank 2 ? ? ? ? 1 ? ? ? 88.2-khz data rate ? use bank 2 ? ? ? ? ? 1 ? ? 96-khz data rate ? use bank 2 ? ? ? ? ? ? 1 ? 176.4-khz data rate ? use bank 2 ? ? ? ? ? ? ? 1 192-khz data rate ? use bank 2 1 1 1 1 1 1 1 1 default
serial control interface register definitions 60 sles120 ? september 2004 TAS5028A 6.15 input mixer registers (0x41 ? 0x48, channels 1 ? 8) input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and 0x48. each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. each gain coefficient is written as a 32-bit word with the upper 4 bits not used. for 8-gain coefficients, the total is 32 bytes. bold indicates the one channel that is passed through the mixer. table 6 ? 16. input mixer registers format (0x41 ? 0x48, channels 1 ? 8) i 2 c subaddress total bytes register fields description of contents default state a_to_ipmix[1] sdin1?left (ch 1) a to input mixer 1 coefficient (default = 1) u (31:28), a_1 (27:24), a_1 (23:16), a_1 (15:8), a_1 (7:0) 0x00, 0x80, 0x00, 0x00 b_to_ipmix[1] sdin1?right (ch 2) b to input mixer 1 coefficient (default = 0) u (31:28), b_1 (27:24), b_1 (23:16), b_1 (15:8), b_1 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[1] sdin2?left (ch 3) c to input mixer 1 coefficient (default = 0) u (31:28), c_1 (27:24), c_1 (23:16), c_1 (15:8), c_1 (7:0) 0x00, 0x00, 0x00, 0x00 0x41 32 d_to_ipmix[1] sdin2?right (ch 4) d to input mixer 1 coefficient (default = 0) u (31:28), d_1 (27:24), d_1 (23:16), d_1 (15:8), d_1 (7:0) 0x00, 0x00, 0x00, 0x00 0x41 32 e_to_ipmix[1] sdin3?left (ch 5) e to input mixer 1 coefficient (default = 0) u (31:28), e_1 (27:24), e_1 (23:16), e_1 (15:8), e_1 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[1] sdin3?right (ch 6) f to input mixer 1 coefficient (default = 0) u (31:28), f_1 (27:24), f_1 (23:16), f_1 (15:8), f_1 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[1] sdin4?left (ch 7) g to input mixer 1 coefficient (default = 0) u (31:28), g_1 (27:24), g_1 (23:16), g_1 (15:8), g_1 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[1] sdin4?right (ch 8) h to input mixer 1 coefficient (default = 0) u (31:28), h_1 (27:24), h_1 (23:16), h_1 (15:8), h_1 (7:0) 0x00, 0x00, 0x00, 0x00 a_to_ipmix[2] sdin1?left (ch 1) a to input mixer 2 coefficient (default = 0) u (31:28), a_2 (27:24), a_2 (23:16), a_2 (15:8), a_2 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[2] sdin1?right (ch 2) b to input mixer 2 coefficient (default = 1) u (31:28), b_2 (27:24), b_2 (23:16), b_2 (15:8), b_2 (7:0) 0x00, 0x80, 0x00, 0x00 c_to_ipmix[2] sdin2?left (ch 3) c to input mixer 2 coefficient (default = 0) u (31:28), c_2(27:24), c_2(23:16), c_2(15:8), c_2(7:0) 0x00, 0x00, 0x00, 0x00 0x42 32 d_to_ipmix[2] sdin2?right (ch 4) d to input mixer 2 coefficient (default = 0) u (31:28), d_2 (27:24), d_2 (23:16), d_2 (15:8), d_2 (7:0) 0x00, 0x00, 0x00, 0x00 0x42 32 e_to_ipmix[2] sdin3?left (ch 5) e to input mixer 2 coefficient (default = 0) u (31:28), e_2 (27:24), e_2 (23:16), e_2 (15:8), e_2 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[2] sdin3?right (ch 6) f to input mixer 2 coefficient (default = 0) u (31:28), f_2 (27:24), f_2 (23:16), f_2 (15:8), f_2 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[2] sdin4?left (ch 7) g to input mixer 2 coefficient (default = 0) u (31:28), g_2 (27:24), g_2 (23:16), g_2 (15:8), g_2 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[2] sdin4?right (ch 8) h to input mixer 2 coefficient (default = 0) u (31:28), h_2 (27:24), h_2 (23:16), h_2 (15:8), h_2 (7:0) 0x00, 0x00, 0x00, 0x00
serial control interface register definitions 61 sles120 ? september 2004 TAS5028A i 2 c subaddress total bytes register fields description of contents default state a_to_ipmix[3] sdin1?left (ch 1) a to input mixer 3 coefficient (default = 0) u (31:28), a_3 (27:24), a_3 (23:16), a_3 (15:8), a_3 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[3] sdin1?right (ch 2) b to input mixer 3 coefficient (default = 0) u (31:28), b_3 (27:24), b_3 (23:16), b_3 (15:8), b_3 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[3] sdin2?left (ch 3) c to input mixer 3 coefficient (default = 1) u (31:28), c_3 (27:24), c_3 (23:16), c_3 (15:8), c_3 (7:0) 0x00, 0x80, 0x00, 0x00 0x43 32 d_to_ipmix[3] sdin2?right (ch 4) d to input mixer 3 coefficient (default = 0) u (31:28), d_3 (27:24), d_3 (23:16), d_3 (15:8), d_3 (7:0) 0x00, 0x00, 0x00, 0x00 0x43 32 e_to_ipmix[3] sdin3?left (ch 5) e to input mixer 3 coefficient (default = 0) u (31:28), e_3 (27:24), e_3 (23:16), e_3 (15:8), e_3 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[3] sdin3?right (ch 6) f to input mixer 3 coefficient (default = 0) u (31:28), f_3 (27:24), f_3 (23:16), f_3 (15:8), f_3 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[3] sdin4?left (ch 7) g to input mixer 3 coefficient (default = 0) u (31:28), g_3 (27:24), g_3 (23:16), g_3 (15:8), g_3 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[3] sdin4?right (ch 8) h to input mixer 3 coefficient (default = 0) u (31:28), h_3 (27:24), h_3 (23:16), h_3 (15:8), h_3 (7:0) 0x00, 0x00, 0x00, 0x00 a_to_ipmix[4] sdin1?left (ch 1) a to input mixer 4 coefficient (default = 0) u (31:28), a_4 (27:24), a_4 (23:16), a_4 (15:8), a_4 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[4] sdin1?right (ch 2) b to input mixer 4 coefficient (default = 0) u (31:28), b_4 (27:24), b_4 (23:16), b_4 (15:8), b_4 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[4] sdin2?left (ch 3) c to input mixer 4 coefficient (default = 0) u (31:28), c_4 (27:24), c_4 (23:16), c_4 (15:8), c_4 (7:0) 0x00, 0x00, 0x00, 0x00 0x44 32 d_to_ipmix[4] sdin2?right (ch 4) d to input mixer 4 coefficient (default = 1) u (31:28), d_4 (27:24), d_4 (23:16), d_4 (15:8), d_4 (7:0) 0x00, 0x80, 0x00, 0x00 0x44 32 e_to_ipmix[4] sdin3?left (ch 5) e to input mixer 4 coefficient (default = 0) u (31:28), e_4 (27:24), e_4 (23:16), e_4 (15:8), e_4 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[4] sdin3?right (ch 6) f to input mixer 4 coefficient (default = 0) u (31:28), f_4 (27:24), f_4 (23:16), f_4 (15:8), f_4 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[4] sdin4?left (ch 7) g to input mixer 4 coefficient (default = 0) u (31:28), g_4 (27:24), g_4 (23:16), g_4 (15:8), g_4 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[4] sdin4?right (ch 8) h to input mixer 4 coefficient (default = 0) u (31:28), h_4 (27:24), h_4 (23:16), h_4 (15:8), h_4 (7:0) 0x00, 0x00, 0x00, 0x00 a_to_ipmix[5] sdin1?left (ch 1) a to input mixer 5 coefficient (default = 0) u (31:28), a_5 (27:24), a_5 (23:16), a_5 (15:8), a_5 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[5] sdin1?right (ch 2) b to input mixer 5 coefficient (default = 0) u (31:28), b_5 (27:24), b_5 (23:16), b_5 (15:8), b_5 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[5] sdin2?left (ch 3) c to input mixer 5 coefficient (default = 0) u (31:28), c_5 (27:24), c_5 (23:16), c_5 (15:8), c_5 (7:0) 0x00, 0x00, 0x00, 0x00 0x45 32 d_to_ipmix[5] sdin2?right (ch 4) d to input mixer 5 coefficient (default = 0) u (31:28), d_5 (27:24), d_5 (23:16), d_5 (15:8), d_5 (7:0) 0x00, 0x00, 0x00, 0x00 0x45 32 e_to_ipmix[5] sdin3?left (ch 5) e to input mixer 5 coefficient (default = 1) u (31:28), e_5 (27:24), e_5 (23:16), e_5 (15:8), e_5 (7:0) 0x00, 0x80, 0x00, 0x00 f_to_ipmix[5] sdin3?right (ch 6) f to input mixer 5 coefficient (default = 0) u (31:28), f_5 (27:24), f_5 (23:16), f_5 (15:8), f_5 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[5] sdin4?left (ch 7) g to input mixer 5 coefficient (default = 0) u (31:28), g_5 (27:24), g_5 (23:16), g_5 (15:8), g_5 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[5] sdin4?right (ch 8) h to input mixer 5 coefficient (default = 0) u (31:28), h_5 (27:24), h_5 (23:16), h_5 (15:8), h_5 (7:0) 0x00, 0x00, 0x00, 0x00
serial control interface register definitions 62 sles120 ? september 2004 TAS5028A i 2 c subaddress total bytes register fields description of contents default state a_to_ipmix[6] sdin1?left (ch 1) a to input mixer 6 coefficient (default = 0) u (31:28), a_6 (27:24), a_6 (23:16), a_6 (15:8), a_6 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[6] sdin1?right (ch 2) b to input mixer 6 coefficient (default = 0) u (31:28), b_6 (27:24), b_6 (23:16), b_6 (15:8), b_6 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[6] sdin2?left (ch 3) c to input mixer 6 coefficient (default = 0) u (31:28), c_6 (27:24), c_6 (23:16), c_6 (15:8), c_6 (7:0) 0x00, 0x00, 0x00, 0x00 0x46 32 d_to_ipmix[6] sdin2?right (ch 4) d to input mixer 6 coefficient (default = 0) u (31:28), d_6 (27:24), d_6 (23:16), d_6 (15:8), d_6 (7:0) 0x00, 0x00, 0x00, 0x00 0x46 32 e_to_ipmix[6] sdin3?left (ch 5) e to input mixer 6 coefficient (default = 0) u (31:28), e_6 (27:24), e_6 (23:16), e_6 (15:8), e_6 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[6] sdin3?right (ch 6) f to input mixer 6 coefficient (default = 1) u (31:28), f_6 (27:24), f_6 (23:16), f_6 (15:8), f_6 (7:0) 0x00, 0x80, 0x00, 0x00 g_to_ipmix[6] sdin4?left (ch 7) g to input mixer 6 coefficient (default = 0) u (31:28), g_6 (27:24), g_6 (23:16), g_6 (15:8), g_6 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[6] sdin4?right (ch 8) h to input mixer 6 coefficient (default = 0) u (31:28), h_6 (27:24), h_6 (23:16), h_6 (15:8), h_6 (7:0) 0x00, 0x00, 0x00, 0x00 a_to_ipmix[7] sdin1?left (ch 1) a to input mixer 7 coefficient (default = 0) u (31:28), a_7 (27:24), a_7 (23:16), a_7 (15:8), a_7 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[7] sdin1?right (ch 2) b to input mixer 7 coefficient (default = 0) u (31:28), b_7 (27:24), b_7 (23:16), b_7 (15:8), b_7 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[7] sdin2?left (ch 3) c to input mixer 7 coefficient (default = 0) u (31:28), c_7 (27:24), c_7 (23:16), c_7 (15:8), c_7 (7:0) 0x00, 0x00, 0x00, 0x00 0x47 32 d_to_ipmix[7] sdin2?right (ch 4) d to input mixer 7 coefficient (default = 0) u (31:28), d_7 (27:24), d_7 (23:16), d_7 (15:8), d_7 (7:0) 0x00, 0x00, 0x00, 0x00 0x47 32 e_to_ipmix[7] sdin3?left (ch 5) e to input mixer 7 coefficient (default = 0) u (31:28), e_7 (27:24), e_7 (23:16), e_7 (15:8), e_7 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[7] sdin3?right (ch 6) f to input mixer 7 coefficient (default = 0) u (31:28), f_7 (27:24), f_7 (23:16), f_7 (15:8), f_7 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[7] sdin4?left (ch 7) g to input mixer 7 coefficient (default = 1) u (31:28), g_7 (27:24), g_7 (23:16), g_7 (15:8), g_7 (7:0) 0x00, 0x80, 0x00, 0x00 h_to_ipmix[7] sdin4?right (ch 8) h to input mixer 7 coefficient (default = 0) u (31:28), h_7 (27:24), h_7 (23:16), h_7 (15:8), h_7 (7:0) 0x00, 0x00, 0x00, 0x00 a_to_ipmix[8] sdin1?left (ch 1) a to input mixer 8 coefficient (default = 0) u (31:28), a_8 (27:24), a_8 (23:16), a_8 (15:8), a_8 (7:0) 0x00, 0x00, 0x00, 0x00 b_to_ipmix[8] sdin1?right (ch 2) b to input mixer 8 coefficient (default = 0) u (31:28), b_8 (27:24), b_8 (23:16), b_8 (15:8), b_8 (7:0) 0x00, 0x00, 0x00, 0x00 c_to_ipmix[8] sdin2?left (ch 3) c to input mixer 8 coefficient (default = 0) u (31:28), c_8 (27:24), c_8 (23:16), c_8 (15:8), c_8 (7:0) 0x00, 0x00, 0x00, 0x00 0x48 32 d_to_ipmix[8] sdin2?right (ch 4) d to input mixer 8 coefficient (default = 0) u (31:28), d_8 (27:24), d_8 (23:16), d_8 (15:8), d_8 (7:0) 0x00, 0x00, 0x00, 0x00 0x48 32 e_to_ipmix[8] sdin3?left (ch 5) e to input mixer 8 coefficient (default = 0) u (31:28), e_8 (27:24), e_8 (23:16), e_8 (15:8), e_8 (7:0) 0x00, 0x00, 0x00, 0x00 f_to_ipmix[8] sdin3?right (ch 6) f to input mixer 8 coefficient (default = 0) u (31:28), f_8 (27:24), f_8 (23:16), f_8 (15:8), f_8 (7:0) 0x00, 0x00, 0x00, 0x00 g_to_ipmix[8] sdin4?left (ch 7) g to input mixer 8 coefficient (default = 0) u (31:28), g_8 (27:24), g_8 (23:16), g_8 (15:8), g_8 (7:0) 0x00, 0x00, 0x00, 0x00 h_to_ipmix[8] sdin4?right (ch 8) h to input mixer 8 coefficient (default = 1) u (31:28), h_8 (27:24), h_8 (23:16), h_8 (15:8), h_8 (7:0) 0x00, 0x80, 0x00, 0x00
serial control interface register definitions 63 sles120 ? september 2004 TAS5028A 6.16 bass and treble bypass register (0x89 ? 0x90, channels 1 ? 8) channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8a, 0x8b, 0x8c,0x8d, 0x8e, 0x8f, and 0x90. eight bytes are written for each channel. each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. each gain coefficient is written as a 32-bit word with the upper four bits not used. table 6 ? 17. bass and treble bypass register format (0x89?0x90) register name total bytes contents initialization value channel bass and treble bypass 8 u 31:28), bypass (27:24), bypass (23:16), bypass (15:8), bypass (7:0) 0x00, 0x80, 0x00, 0x00 channel bass and treble inline 8 u (31:28), inline (27:24), inline (23:16), inline (15:8), inline (7:0) 0x00, 0x00, 0x00, 0x00 6.17 8x2 output mixer registers (0xaa ? 0xaf) output mixers for channels 1?6 map to registers 0xaa ? 0xaf. total data per register is 8 bytes. table 6 ? 18. output mixer control register format (upper 4 bytes) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 select channel 1 to output mixer 0 0 0 1 select channel 2 to output mixer 0 0 1 0 select channel 3 to output mixer 0 0 1 1 select channel 4 to output mixer 0 1 0 0 select channel 5 to output mixer 0 1 0 1 select channel 6 to output mixer 0 1 1 0 select channel 7 to output mixer 0 1 1 1 select channel 8 to output mixer g27 g26 g25 g24 selected channel gain (upper 4 bits) d23 d22 d21 d20 d19 d18 d17 d16 function g23 g22 g21 g20 g19 g18 g17 g16 selected channel gain (continued) d15 d14 d13 d12 d11 d10 d9 d8 function g15 g14 g13 g12 g11 g10 g9 g8 selected channel gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 function g7 g6 g5 g4 g3 g2 g1 g0 selected channel gain (lower 8 bits)
serial control interface register definitions 64 sles120 ? september 2004 TAS5028A table 6 ? 19. output mixer control (lower 4 bytes) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 select channel 1 to output mixer 0 0 0 1 select channel 2 to output mixer 0 0 1 0 select channel 3 to output mixer 0 0 1 1 select channel 4 to output mixer 0 1 0 0 select channel 5 to output mixer 0 1 0 1 select channel 6 to output mixer 0 1 1 0 select channel 7 to output mixer 0 1 1 1 select channel 8 to output mixer g27 g26 g25 g24 selected channel gain (upper 4 bits) d23 d22 d21 d20 d19 d18 d17 d16 function g23 g22 g21 g20 g19 g18 g17 g16 selected channel gain (continued) d15 d14 d13 d12 d11 d10 d9 d8 function g15 g14 g13 g12 g11 g10 g9 g8 selected channel gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 function g7 g6 g5 g4 g3 g2 g1 g0 selected channel gain (lower 8 bits) 6.18 8x3 output mixer registers (0xb0 ? 0xb1) output mixers for channels 7 and 8 map to registers 0xb0 and 0xb1. total data per register is 12 bytes. table 6 ? 20. output mixer control (upper 4 bytes) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 select channel 1 to output mixer 0 0 0 1 select channel 2 to output mixer 0 0 1 0 select channel 3 to output mixer 0 0 1 1 select channel 4 to output mixer 0 1 0 0 select channel 5 to output mixer 0 1 0 1 select channel 6 to output mixer 0 1 1 0 select channel 7 to output mixer 0 1 1 1 select channel 8 to output mixer g27 g26 g25 g24 selected channel gain (upper 4 bits) d23 d22 d21 d20 d19 d18 d17 d16 function g23 g22 g21 g20 g19 g18 g17 g16 selected channel gain (continued) d15 d14 d13 d12 d11 d10 d9 d8 function g15 g14 g13 g12 g11 g10 g9 g8 selected channel gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 function g7 g6 g5 g4 g3 g2 g1 g0 selected channel gain (lower 8 bits)
serial control interface register definitions 65 sles120 ? september 2004 TAS5028A table 6 ? 21. output mixer control (middle 4 bytes) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 select channel 1 to output mixer 0 0 0 1 select channel 2 to output mixer 0 0 1 0 select channel 3 to output mixer 0 0 1 1 select channel 4 to output mixer 0 1 0 0 select channel 5 to output mixer 0 1 0 1 select channel 6 to output mixer 0 1 1 0 select channel 7 to output mixer 0 1 1 1 select channel 8 to output mixer g27 g26 g25 g24 selected channel gain (upper 4 bits) d23 d22 d21 d20 d19 d18 d17 d16 function g23 g22 g21 g20 g19 g18 g17 g16 selected channel gain (continued) d15 d14 d13 d12 d11 d10 d9 d8 function g15 g14 g13 g12 g11 g10 g9 g8 selected channel gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 function g7 g6 g5 g4 g3 g2 g1 g0 selected channel gain (lower 8 bits) table 6 ? 22. output mixer control (lower 4 bytes) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 select channel 1 to output mixer 0 0 0 1 select channel 2 to output mixer 0 0 1 0 select channel 3 to output mixer 0 0 1 1 select channel 4 to output mixer 0 1 0 0 select channel 5 to output mixer 0 1 0 1 select channel 6 to output mixer 0 1 1 0 select channel 7 to output mixer 0 1 1 1 select channel 8 to output mixer g27 g26 g25 g24 selected channel gain (upper 4 bits) d23 d22 d21 d20 d19 d18 d17 d16 function g23 g22 g21 g20 g19 g18 g17 g16 selected channel gain (continued) d15 d14 d13 d12 d11 d10 d9 d8 function g15 g14 g13 g12 g11 g10 g9 g8 selected channel gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 function g7 g6 g5 g4 g3 g2 g1 g0 selected channel gain (lower 8 bits) 6.19 volume treble and bass slew rates (0xd0) table 6 ? 23. volume gain update rate (slew rate) d31?d10 d9 d8 function 0 0 0 512 step update at 4 fs, 42.6 ms at 48 khz 0 0 1 1024 step update at 4 fs, 85.3 ms at 48 khz 0 1 0 2048 step update at 4 fs, 170 ms at 48 khz 0 1 1 2048 step update at 4 fs, 170 ms at 48 khz
serial control interface register definitions 66 sles120 ? september 2004 TAS5028A table 6 ? 24. treble and bass gain step size (slew rate) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 no operation 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 minimum rate ? updates every 0.083 ms (every lrclk at 48 khz) 0 0 1 0 0 0 0 0 update ever 0.67 ms (32 lrclks at 48 khz) 0 0 1 1 1 1 1 1 default rate ? updates every 1.31 ms (63 lrclks at 48 khz). this is the maximum constant time that can be set for all sample rates. 1 1 1 1 1 1 1 1 minimum rate ? updates every 5.08 ms (every 255 lrclks at 48 khz) 6.20 volume registers (0xd1 ? 0xd9) channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, and 0xd8. master volume is mapped into register 0xd9. bits d31 ? d12 are don?t care . table 6 ? 25. volume registers d31 d30 d29 d28 d27 d26 d25 d24 function unused bits d23 d22 d21 d20 d19 d18 d17 d16 function unused bits d15 d14 d13 d12 d11 d10 d9 d8 function v11 v10 v9 v8 volume d7 d6 d5 d4 d3 d2 d1 d0 function v7 v6 v5 v4 v3 v2 v1 v0 volume
serial control interface register definitions 67 sles120 ? september 2004 TAS5028A table 6 ? 26. master and individual volume controls volume index (h) gain/index expected actual 001 17.75 17.81 17.81 002 17.5 17.56 17.56 003 17.25 17.31 17.31 004 17 17.06 17.06 005 16.75 16.81 16.81 006 16.5 16.56 16.56 007 16.25 16.31 16.31 008 16 16.05 16.05 009 15.75 15.8 15.8 00a 15.5 15.55 15.55 00b 15.25 15.3 15.3 00c 15 15.05 15.05 00d 14.75 14.8 14.8 00e 14.5 14.55 14.55 00f 14.25 14.3 14.3 010 14 14.05 14.05 044 1 1 1 045 0.75 0.75 0.75 046 0.5 0.5 0.5 047 0.25 0.25 0.25 048 0 0 0 049 ?0.25 ?0.25 ?0.25 04a ?0.5 ?0.5 ?0.5 04b ?0.75 ?0.75 ?0.75 04c ?1 ?1 ?1 240 ?126 ?126.43 ?126.43 241 ?126.25 ?126.68 ?126.99 242 ?126.5 ?126.93 ?126.99 243 ?126.75 ?127.19 ?127.59 244 ?127 ?127.44 ?127.59 245 mute mute mute to 3ff mute mute mute 6.21 bass filter set register (0xda) bits d31?d27, d23?d19, d15?d11, and d7?d3 are don?t care . table 6 ? 27. channel 8 sub woofer d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 bass filter set 1 0 0 0 0 0 0 1 0 bass filter set 2 0 0 0 0 0 1 1 1 bass filter set 3 0 0 0 0 0 1 0 0 bass filter set 4 0 0 0 0 0 1 0 1 bass filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal
serial control interface register definitions 68 sles120 ? september 2004 TAS5028A table 6 ? 28. channel 6 and 5 (right and left lineout in six channel configuration right and left surround in eight channel configuration) d23 d22 d21 d20 d19 d18 d17 d16 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 bass filter set 1 0 0 0 0 0 0 1 0 bass filter set 2 0 0 0 0 0 1 1 1 bass filter set 3 0 0 0 0 0 1 0 0 bass filter set 4 0 0 0 0 0 1 0 1 bass filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal table 6 ? 29. channel 4 and 3 (right and left rear) d15 d14 d13 d12 d11 d10 d9 d8 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 bass filter set 1 0 0 0 0 0 0 1 0 bass filter set 2 0 0 0 0 0 1 1 1 bass filter set 3 0 0 0 0 0 1 0 0 bass filter set 4 0 0 0 0 0 1 0 1 bass filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal table 6 ? 30. channel 7, 2, 1 (center, right front, and left front) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 bass filter set 1 0 0 0 0 0 0 1 0 bass filter set 2 0 0 0 0 0 1 1 1 bass filter set 3 0 0 0 0 0 1 0 0 bass filter set 4 0 0 0 0 0 1 0 1 bass filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal 6.22 bass filter index register (0xdb) index values above 0x24 are invalid. table 6 ? 31. bass filter index register i 2 c subaddress total bytes register name description of contents default state 0xdb bass filter index (bfi) 4 ch8_bfi (31:24), ch65_bfi (23:16), ch43_bfi (15:8), ch721_bfi (7:0) 0x12, 0x12, 0x12, 0x12,
serial control interface register definitions 69 sles120 ? september 2004 TAS5028A table 6 ? 32. bass filter index table treble index value adjustment (db) treble index value adjustment (db) 0x00 18 0x13 ?1 0x01 17 0x14 ?2 0x02 16 0x15 ?3 0x03 15 0x16 ?4 0x04 14 0x17 ?5 0x05 13 0x18 ?6 0x06 12 0x19 ?7 0x07 11 0x1a ?8 0x08 10 0x1b ?9 0x09 9 0x1c ?10 0x0a 8 0x1d ?11 0x0b 7 0x1e ?12 0x0c 6 0x1f ?13 0x0d 5 0x20 ?14 0x0e 4 0x21 ?15 0x0f 3 0x22 ?16 0x10 2 0x23 ?17 0x11 1 0x24 ?18 0x12 0 6.23 treble filter set register (0xdc) bits d31?d27 are don?t care . table 6 ? 33. channel 8 sub woofer d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 treble filter set 1 0 0 0 0 0 0 1 0 treble filter set 2 0 0 0 0 0 1 1 1 treble filter set 3 0 0 0 0 0 1 0 0 treble filter set 4 0 0 0 0 0 1 0 1 treble filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal table 6 ? 34. channel 6 and 5 (right and left lineout in six channel configuration or right and left surround in eight channel configuration) d23 d22 d21 d20 d19 d18 d17 d16 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 treble filter set 1 0 0 0 0 0 0 1 0 treble filter set 2 0 0 0 0 0 1 1 1 treble filter set 3 0 0 0 0 0 1 0 0 treble filter set 4 0 0 0 0 0 1 0 1 treble filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal
serial control interface register definitions 70 sles120 ? september 2004 TAS5028A table 6 ? 35. channel 4 and 3 (right and left rear) d15 d14 d13 d12 d11 d10 d9 d8 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 treble filter set 1 0 0 0 0 0 0 1 0 treble filter set 2 0 0 0 0 0 1 1 1 treble filter set 3 0 0 0 0 0 1 0 0 treble filter set 4 0 0 0 0 0 1 0 1 treble filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal table 6 ? 36. channel 7, 2, 1 (center, right front, and left front) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 no change 0 0 0 0 0 0 0 1 treble filter set 1 0 0 0 0 0 0 1 0 treble filter set 2 0 0 0 0 0 1 1 1 treble filter set 3 0 0 0 0 0 1 0 0 treble filter set 4 0 0 0 0 0 1 0 1 treble filter set 5 0 0 0 0 0 1 1 0 illegal 0 0 0 0 0 1 1 1 illegal 6.24 treble filter index (0xdd) index values above 0x24 are invalid. table 6 ? 37. treble filter index register i 2 c subaddress total bytes register name description of contents default state 0xdd treble filter index (tfi) 4 ch8_tfi (31:24), ch65_tfi (23:16), ch43_tfi (15:8), ch721_tfi (7:0) 0x12,0x12,0x12,0x12 table 6 ? 38. treble filter index treble index value adjustment (db) treble index value adjustment (db) 0x00 18 0x13 ?1 0x01 17 0x14 ?2 0x02 16 0x15 ?3 0x03 15 0x16 ?4 0x04 14 0x17 ?5 0x05 13 0x18 ?6 0x\06 12 0x19 ?7 0x07 11 0x1a ?8 0x08 10 0x1b ?9 0x09 9 0x1c ?10 0x0a 8 0x1d ?11 0x0b 7 0x1e ?12 0x0c 6 0x1f ?13 0x0d 5 0x20 ?14 0x0e 4 0x21 ?15 0x0f 3 0x22 ?16 0x10 2 0x23 ?17 0x11 1 0x24 ?18 0x12 0
serial control interface register definitions 71 sles120 ? september 2004 TAS5028A 6.25 am mode register (0xde) bits d31?d21 are don?t care . table 6 ? 39. am mode register d31 d30 d29 d28 d27 d26 d25 d24 function unused bits d23 d22 d21 d20 d19 d18 d17 d16 function 0 ? ? ? ? am mode disabled 1 ? ? ? ? am mode enabled ? 0 0 ? ? select sequence 1 ? 0 1 ? ? select sequence 2 ? 1 0 ? ? select sequence 3 ? 1 1 ? ? select sequence 4 ? ? ? 0 ? if frequency 455 ? ? ? 1 ? if frequency 262.5 ? ? ? ? 0 use bcd tuned frequency ? ? ? ? 1 use binary tuned frequency table 6 ? 40. am tuned frequency register in bcd mode (lower 2 bytes of 0xde) d15 d14 d13 d12 d11 d10 d9 d8 function 0 0 0 b0 ? ? ? ? bcd frequency (1000s khz) ? ? ? ? b3 b2 b1 b0 bcd frequency (100s khz) 0 0 0 0 0 0 0 0 default value d7 d6 d5 d4 d3 d2 d1 d0 function b3 b2 b1 b0 ? ? ? ? bcd frequency (10s khz) ? ? ? ? b3 b2 b1 b0 bcd frequency (1s khz) 0 0 0 0 0 0 0 0 default value table 6 ? 41. am tuned frequency register in binary mode (lower 2 bytes of 0xde) d15 d14 d13 d12 d11 d10 d9 d8 function 0 0 0 0 0 b10 b9 b8 binary frequency (upper 3 bits) 0 0 0 0 0 0 0 0 default value d7 d6 d5 d4 d3 d2 d1 d0 function b7 b6 b5 b4 b3 b2 b1 b0 binary frequency (lower 8 bits) 0 0 0 0 0 0 0 0 default value 6.26 general control register (0xe0) bits d31?d4 are zero. bit d0 is don?t care . table 6 ? 42. general control register d31 ? d4 d3 d2 d1 d0 function 0 ? 0 /8 channel configuration 0 ? 1 6 channel configuration 6.27 incremental multiple write append register (0xfe) this is a special register used to append data to a previously opened register.
TAS5028A example application schematic 73 sles120 ? september 2004 TAS5028A 7 TAS5028A example application schematic the following page contains an example application schematic for the TAS5028A.
5 5 4 4 3 3 2 2 1 1 d d c c b b a a right back surround speaker output left back surround speaker output subwoofer speaker output center speaker output right surround speaker output left surround speaker output left speaker output line output headphone output TAS5028A example application schematic right speaker output (circuit is subject to change without notice) ch1 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning ch4 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning ch7 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning ch5 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning left + right line out 2 channel line out (tlv272) +3.3v +5.0v pwm_p_l pwm_m_l pwm_p_r pwm_m_r out_l out_r /oe ch8 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning psu and interface logic +3.3v +5.0v gvdd v-hbridge /reset psvc_mcpu /reset_TAS5028A /otw_tas5121 /otw /bknd_err /bknd_err_TAS5028A /sd1_tas5121 /sd1 conf_sel /valid /valid_ch5+ch6 /line_out_enable /sd2 /sd2_tas5121 psvc_TAS5028A ch3 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning ch2 tas5121 h-bridge output stage /shutdown_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning ch6 tas5121 h-bridge output stage /sd1_tas5121 pwm_p pwm_m /valid out_1 out_2 gvdd v-hbridge /temp_warning left + right headphone 2 channel h eadp hone design (tpa112) pwm_hpp_r pwm_hpm_r out_l out_r +5.0v pwm_hpp_l pwm_hpm_l out_gnd +3.3v gnd gnd +3.3v gvdd v-hbridge gvdd v-hbridge gvdd v-hbridge gvdd v-hbridge v-hbridge gvdd v-hbridge gvdd v-hbridge gvdd v-hbridge gvdd +3.3v gnd +3.3v gnd +5.0v +3.3v +5.0v gvdd v-hbridge +5.0v +3.3v gnd gnd c25 220nf 2 1 j600 1 2 r21 1m 1 2 c14 100nf 2 1 c13 10nf 2 1 c17 100nf 2 1 c20 100nf 2 1 j951 phono socket 2 3 4 1 r13 3.30r 1 2 x10 13.5mhz j100 1 2 j400 1 2 j700 1 2 j800 1 2 c15 100nf 2 1 r12 2r 1 2 c11 100nf 2 1 c10 10nf 2 1 c29 100nf 2 1 r18 1r 1 2 j500 1 2 r20 22.0r 1 2 r10 200r 1 2 c28 15pf 2 1 r11 200r 1 2 c27 15pf 2 1 j300 1 2 c23 10uf 1 2 c21 100nf 2 1 c18 1nf 1 2 c26 10uf 1 2 j950 phono socket 2 3 4 1 c16 10uf 1 2 c12 100nf 2 1 j200 1 2 c24 100nf 2 1 u10 TAS5028A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 22 vra_pll pll_flt_ret pll_fltm pll_fltp avss avss vrd_pll avss_pll avdd_pll vbgap reset hp_sel pdn mute dvdd dvss vr_dpll osc_cap xtl_out xtl_in reserved reserved sda scl lrclk sclk sdin4 sdin3 sdin2 sdin1 psvc vr_pwm pwm_p_4 pwm_m_4 pwm_p_3 pwm_m_3 pwm_p_2 pwm_m_2 pwm_p_1 pwm_m_1 vaild dvss bknd_err dvdd dvss dvss vr_dig reserved mclk pwm_hppr pwm_hpmr pwm_hppl pwm_hpml pwm_p_6 pwm_m_6 pwm_p_5 pwm_m_5 dvdd_pwm dvss_pwm pwm_p_8 pwm_m_8 pwm_p_7 pwm_m_7 reserved r14 1r 1 2 c22 100nf 2 1 j900 mini-jack (3.5mm) 2 4 3 1 c19 10uf 1 2 /valid_ch5+ch6 /valid /valid /valid /valid /valid /valid /reset_TAS5028A /reset /bknd_err /bknd_err_TAS5028A /otw_tas5121 /otw /sd1_tas5121 /sd1 /sd2_tas5121 /sd2 /valid_ch5+ch6 /valid conf_sel /valid_ch5+ch6 /sd1_tas5121 /otw_tas5121 /sd1_tas5121 /otw_tas5121 /sd2_tas5121 /otw_tas5121 /sd2_tas5121 /otw_tas5121 /sd1_tas5121 /otw_tas5121 /sd2_tas5121 /otw_tas5121 /sd2_tas5121 /otw_tas5121 /sd2_tas5121 /otw_tas5121 /line_out_enable psvc_TAS5028A psvc_mcpu /line_out_enable /bknd_err_TAS5028A /hp_sel /pdn_TAS5028A /valid /mute_TAS5028A mclk /reset_TAS5028A scl psvc_TAS5028A sda lrclk sdin4 sclk sdin3 sdin2 sdin1
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TAS5028Apag active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr TAS5028Apagg4 active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr TAS5028Apagr active tqfp pag 64 1500 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr TAS5028Apagrg4 active tqfp pag 64 1500 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 19-jun-2007 addendum-page 1
tape and reel box information device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TAS5028Apagr pag 64 site 60 330 24 13.0 13.0 1.5 16 24 q2 package materials information www.ti.com 4-oct-2007 pack materials-page 1
device package pins site length (mm) width (mm) height (mm) TAS5028Apagr pag 64 site 60 367.0 367.0 45.0 package materials information www.ti.com 4-oct-2007 pack materials-page 2
mechanical data mtqf006a january 1995 revised december 1996 post office box 655303 ? dallas, texas 75265 pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

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